* [PATCH V4 0/5] Add initial support for MA35D1 SoC
@ 2022-05-10 3:25 Jacky Huang
2022-05-10 3:25 ` [PATCH V4 1/5] dt-bindings: clock: add binding for MA35D1 clock controller Jacky Huang
` (5 more replies)
0 siblings, 6 replies; 26+ messages in thread
From: Jacky Huang @ 2022-05-10 3:25 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-clk, linux-arm-kernel, ychuang570808
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc,
cfli0, Jacky Huang
This patch series adds initial support for Nuvoton MA35D1 SoC,
include initial dts and clock controller binding.
v4:
- patch 4/5 is a resend
- Fixed dt_binding_check errors of nuvoton,ma35d1-clk.yaml
- Modify ma35d1.dtsi
1. Add a node hxt_24m
2. Fixed the base address of gic node
3. Add clocks and clock-names to clock node
- Fixed borad binding mistakes of nuvoton.yaml
v3:
- added patch 4/5 and 5/5
- introduce CONFIG_ARCH_NUVOTON option
- add initial bindings for Nuvoton Platform boards
- fixed coding style problem of nuvoton,ma35d1-clk.h
- added CAPLL to clock-controller node
- modify the chosen node of ma35d1-evb.dts
- modify clock yaml "clk-pll-mode" to "nuvoton,clk-pll-mode"
v2:
- fixed dt_binding_check failed of nuvoton,ma35d1-clk.yaml
Jacky Huang (5):
dt-bindings: clock: add binding for MA35D1 clock controller
dt-bindings: clock: Document MA35D1 clock controller bindings
arm64: dts: nuvoton: Add initial support for MA35D1
arm64: Kconfig: nuvoton: Introduce CONFIG_ARCH_NUVOTON
dt-bindings: arm: Add initial bindings for Nuvoton Platform
.../devicetree/bindings/arm/nuvoton.yaml | 31 +++
.../bindings/clock/nuvoton,ma35d1-clk.yaml | 74 +++++
arch/arm64/Kconfig.platforms | 10 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/nuvoton/Makefile | 2 +
arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts | 24 ++
arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 120 ++++++++
.../dt-bindings/clock/nuvoton,ma35d1-clk.h | 260 ++++++++++++++++++
8 files changed, 522 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/nuvoton.yaml
create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml
create mode 100644 arch/arm64/boot/dts/nuvoton/Makefile
create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts
create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
create mode 100644 include/dt-bindings/clock/nuvoton,ma35d1-clk.h
--
2.30.2
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH V4 1/5] dt-bindings: clock: add binding for MA35D1 clock controller
2022-05-10 3:25 [PATCH V4 0/5] Add initial support for MA35D1 SoC Jacky Huang
@ 2022-05-10 3:25 ` Jacky Huang
2022-05-10 3:25 ` [PATCH V4 2/5] dt-bindings: clock: Document MA35D1 clock controller bindings Jacky Huang
` (4 subsequent siblings)
5 siblings, 0 replies; 26+ messages in thread
From: Jacky Huang @ 2022-05-10 3:25 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-clk, linux-arm-kernel, ychuang570808
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc,
cfli0, Jacky Huang
Add the dt-bindings header for Nuvoton MA35D1, that gets shared
between the clock controller and clock references in the dts.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../dt-bindings/clock/nuvoton,ma35d1-clk.h | 260 ++++++++++++++++++
1 file changed, 260 insertions(+)
create mode 100644 include/dt-bindings/clock/nuvoton,ma35d1-clk.h
diff --git a/include/dt-bindings/clock/nuvoton,ma35d1-clk.h b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h
new file mode 100644
index 000000000000..063002384c00
--- /dev/null
+++ b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h
@@ -0,0 +1,260 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corporation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H
+#define __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H
+
+/* Clock Sources */
+/* External and Internal oscillator clocks */
+#define HXT 0
+#define HXT_GATE 1
+#define LXT 2
+#define LXT_GATE 3
+#define HIRC 4
+#define HIRC_GATE 5
+#define LIRC 6
+#define LIRC_GATE 7
+
+/* PLLs */
+#define CAPLL 8
+#define SYSPLL 9
+#define DDRPLL 10
+#define APLL 11
+#define EPLL 12
+#define VPLL 13
+
+/* EPLL Divider */
+#define EPLL_DIV2 14
+#define EPLL_DIV4 15
+#define EPLL_DIV8 16
+
+/* CA35 CPU Clock, System Clock, AXI, HCLK and PCLK */
+#define CA35CLK_MUX 17
+#define AXICLK_DIV2 18
+#define AXICLK_DIV4 19
+#define AXICLK_MUX 20
+#define SYSCLK0_MUX 21
+#define SYSCLK1_MUX 22
+#define SYSCLK1_DIV2 23
+#define HCLK0 24
+#define HCLK1 25
+#define HCLK2 26
+#define PCLK0 27
+#define PCLK1 28
+#define PCLK2 29
+#define HCLK3 30
+#define PCLK3 31
+#define PCLK4 32
+
+/* Peripheral clocks */
+/* AXI and AHB Clocks */
+#define USBPHY0 33
+#define USBPHY1 34
+#define DDR0_GATE 35
+#define DDR6_GATE 36
+#define CAN0_MUX 37
+#define CAN0_DIV 38
+#define CAN0_GATE 39
+#define CAN1_MUX 40
+#define CAN1_DIV 41
+#define CAN1_GATE 42
+#define CAN2_MUX 43
+#define CAN2_DIV 44
+#define CAN2_GATE 45
+#define CAN3_MUX 46
+#define CAN3_DIV 47
+#define CAN3_GATE 48
+#define SDH0_MUX 49
+#define SDH0_GATE 50
+#define SDH1_MUX 51
+#define SDH1_GATE 52
+#define NAND_GATE 53
+#define USBD_GATE 54
+#define USBH_GATE 55
+#define HUSBH0_GATE 56
+#define HUSBH1_GATE 57
+#define GFX_MUX 58
+#define GFX_GATE 59
+#define VC8K_GATE 60
+#define DCU_MUX 61
+#define DCU_GATE 62
+#define DCUP_DIV 63
+#define EMAC0_GATE 64
+#define EMAC1_GATE 65
+#define CCAP0_MUX 66
+#define CCAP0_DIV 67
+#define CCAP0_GATE 68
+#define CCAP1_MUX 69
+#define CCAP1_DIV 70
+#define CCAP1_GATE 71
+#define PDMA0_GATE 72
+#define PDMA1_GATE 73
+#define PDMA2_GATE 74
+#define PDMA3_GATE 75
+#define WH0_GATE 76
+#define WH1_GATE 77
+#define HWS_GATE 78
+#define EBI_GATE 79
+#define SRAM0_GATE 80
+#define SRAM1_GATE 81
+#define ROM_GATE 82
+#define TRA_GATE 83
+#define DBG_MUX 84
+#define DBG_GATE 85
+#define CKO_MUX 86
+#define CKO_DIV 87
+#define CKO_GATE 88
+#define GTMR_GATE 89
+#define GPA_GATE 90
+#define GPB_GATE 91
+#define GPC_GATE 92
+#define GPD_GATE 93
+#define GPE_GATE 94
+#define GPF_GATE 95
+#define GPG_GATE 96
+#define GPH_GATE 97
+#define GPI_GATE 98
+#define GPJ_GATE 99
+#define GPK_GATE 100
+#define GPL_GATE 101
+#define GPM_GATE 102
+#define GPN_GATE 103
+
+/* APB Clocks */
+#define TMR0_MUX 104
+#define TMR0_GATE 105
+#define TMR1_MUX 106
+#define TMR1_GATE 107
+#define TMR2_MUX 108
+#define TMR2_GATE 109
+#define TMR3_MUX 110
+#define TMR3_GATE 111
+#define TMR4_MUX 112
+#define TMR4_GATE 113
+#define TMR5_MUX 114
+#define TMR5_GATE 115
+#define TMR6_MUX 116
+#define TMR6_GATE 117
+#define TMR7_MUX 118
+#define TMR7_GATE 119
+#define TMR8_MUX 120
+#define TMR8_GATE 121
+#define TMR9_MUX 122
+#define TMR9_GATE 123
+#define TMR10_MUX 124
+#define TMR10_GATE 125
+#define TMR11_MUX 126
+#define TMR11_GATE 127
+#define UART0_MUX 128
+#define UART0_DIV 129
+#define UART0_GATE 130
+#define UART1_MUX 131
+#define UART1_DIV 132
+#define UART1_GATE 133
+#define UART2_MUX 134
+#define UART2_DIV 135
+#define UART2_GATE 136
+#define UART3_MUX 137
+#define UART3_DIV 138
+#define UART3_GATE 139
+#define UART4_MUX 140
+#define UART4_DIV 141
+#define UART4_GATE 142
+#define UART5_MUX 143
+#define UART5_DIV 144
+#define UART5_GATE 145
+#define UART6_MUX 146
+#define UART6_DIV 147
+#define UART6_GATE 148
+#define UART7_MUX 149
+#define UART7_DIV 150
+#define UART7_GATE 151
+#define UART8_MUX 152
+#define UART8_DIV 153
+#define UART8_GATE 154
+#define UART9_MUX 155
+#define UART9_DIV 156
+#define UART9_GATE 157
+#define UART10_MUX 158
+#define UART10_DIV 159
+#define UART10_GATE 160
+#define UART11_MUX 161
+#define UART11_DIV 162
+#define UART11_GATE 163
+#define UART12_MUX 164
+#define UART12_DIV 165
+#define UART12_GATE 166
+#define UART13_MUX 167
+#define UART13_DIV 168
+#define UART13_GATE 169
+#define UART14_MUX 170
+#define UART14_DIV 171
+#define UART14_GATE 172
+#define UART15_MUX 173
+#define UART15_DIV 174
+#define UART15_GATE 175
+#define UART16_MUX 176
+#define UART16_DIV 177
+#define UART16_GATE 178
+#define RTC_GATE 179
+#define DDR_GATE 180
+#define KPI_MUX 181
+#define KPI_DIV 182
+#define KPI_GATE 183
+#define I2C0_GATE 184
+#define I2C1_GATE 185
+#define I2C2_GATE 186
+#define I2C3_GATE 187
+#define I2C4_GATE 188
+#define I2C5_GATE 189
+#define QSPI0_MUX 190
+#define QSPI0_GATE 191
+#define QSPI1_MUX 192
+#define QSPI1_GATE 193
+#define SMC0_MUX 194
+#define SMC0_DIV 195
+#define SMC0_GATE 196
+#define SMC1_MUX 197
+#define SMC1_DIV 198
+#define SMC1_GATE 199
+#define WDT0_MUX 200
+#define WDT0_GATE 201
+#define WDT1_MUX 202
+#define WDT1_GATE 203
+#define WDT2_MUX 204
+#define WDT2_GATE 205
+#define WWDT0_MUX 206
+#define WWDT1_MUX 207
+#define WWDT2_MUX 208
+#define EPWM0_GATE 209
+#define EPWM1_GATE 210
+#define EPWM2_GATE 211
+#define I2S0_MUX 212
+#define I2S0_GATE 213
+#define I2S1_MUX 214
+#define I2S1_GATE 215
+#define SSMCC_GATE 216
+#define SSPCC_GATE 217
+#define SPI0_MUX 218
+#define SPI0_GATE 219
+#define SPI1_MUX 220
+#define SPI1_GATE 221
+#define SPI2_MUX 222
+#define SPI2_GATE 223
+#define SPI3_MUX 224
+#define SPI3_GATE 225
+#define ECAP0_GATE 226
+#define ECAP1_GATE 227
+#define ECAP2_GATE 228
+#define QEI0_GATE 229
+#define QEI1_GATE 230
+#define QEI2_GATE 231
+#define ADC_DIV 232
+#define ADC_GATE 233
+#define EADC_DIV 234
+#define EADC_GATE 235
+#define CLK_MAX_IDX 236
+
+#endif /* __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H */
--
2.30.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V4 2/5] dt-bindings: clock: Document MA35D1 clock controller bindings
2022-05-10 3:25 [PATCH V4 0/5] Add initial support for MA35D1 SoC Jacky Huang
2022-05-10 3:25 ` [PATCH V4 1/5] dt-bindings: clock: add binding for MA35D1 clock controller Jacky Huang
@ 2022-05-10 3:25 ` Jacky Huang
2022-05-12 14:04 ` Krzysztof Kozlowski
2022-05-10 3:25 ` [PATCH V4 3/5] arm64: dts: nuvoton: Add initial support for MA35D1 Jacky Huang
` (3 subsequent siblings)
5 siblings, 1 reply; 26+ messages in thread
From: Jacky Huang @ 2022-05-10 3:25 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-clk, linux-arm-kernel, ychuang570808
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc,
cfli0, Jacky Huang
Add documentation to describe Nuvoton MA35D1 clock driver bindings.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/clock/nuvoton,ma35d1-clk.yaml | 74 +++++++++++++++++++
1 file changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml
diff --git a/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml
new file mode 100644
index 000000000000..97af7947b6f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 Clock Control Module Binding
+
+maintainers:
+ - Chi-Fang Li <cfli0@nuvoton.com>
+ - Jacky Huang <ychuang3@nuvoton.com>
+
+description: |
+ The MA35D1 clock controller generates clocks for the whole chip,
+ including system clocks and all peripheral clocks.
+
+ See also:
+ include/dt-bindings/clock/ma35d1-clk.h
+
+properties:
+ compatible:
+ const: nuvoton,ma35d1-clk
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ items:
+ - description: External 24MHz crystal
+
+ clock-names:
+ items:
+ - const: hxt_24m
+
+ assigned-clocks:
+ maxItems: 5
+
+ assigned-clock-rates:
+ maxItems: 5
+
+ nuvoton,clk-pll-mode:
+ description:
+ A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
+ EPLL, and VPLL in sequential. The operation mode value 0 is for
+ integer mode, 1 is for fractional mode, and 2 is for spread
+ spectrum mode.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 5
+ items:
+ minimum: 0
+ maximum: 2
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+
+ clk: clock-controller@40460200 {
+ compatible = "nuvoton,ma35d1-clk";
+ reg = <0x0 0x40460200 0x0 0x100>;
+ #clock-cells = <1>;
+ clocks = <&hxt_24m>;
+ clock-names = "HXT_24MHz";
+ };
+...
--
2.30.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V4 3/5] arm64: dts: nuvoton: Add initial support for MA35D1
2022-05-10 3:25 [PATCH V4 0/5] Add initial support for MA35D1 SoC Jacky Huang
2022-05-10 3:25 ` [PATCH V4 1/5] dt-bindings: clock: add binding for MA35D1 clock controller Jacky Huang
2022-05-10 3:25 ` [PATCH V4 2/5] dt-bindings: clock: Document MA35D1 clock controller bindings Jacky Huang
@ 2022-05-10 3:25 ` Jacky Huang
2022-05-10 7:01 ` Arnd Bergmann
2022-05-12 14:10 ` Krzysztof Kozlowski
2022-05-10 3:25 ` [PATCH V4 4/5] arm64: Kconfig: nuvoton: Introduce CONFIG_ARCH_NUVOTON Jacky Huang
` (2 subsequent siblings)
5 siblings, 2 replies; 26+ messages in thread
From: Jacky Huang @ 2022-05-10 3:25 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-clk, linux-arm-kernel, ychuang570808
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc,
cfli0, Jacky Huang
Add the initial device tree files for Nuvoton MA35D1 Soc.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/nuvoton/Makefile | 2 +
arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts | 24 +++++
arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 120 +++++++++++++++++++++
4 files changed, 147 insertions(+)
create mode 100644 arch/arm64/boot/dts/nuvoton/Makefile
create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts
create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 1ba04e31a438..7b107fa7414b 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -19,6 +19,7 @@ subdir-y += lg
subdir-y += marvell
subdir-y += mediatek
subdir-y += microchip
+subdir-y += nuvoton
subdir-y += nvidia
subdir-y += qcom
subdir-y += realtek
diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile
new file mode 100644
index 000000000000..e1e0c466bf5e
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_NUVOTON) += ma35d1-evb.dtb
diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts
new file mode 100644
index 000000000000..95f0facb0476
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for MA35D1 Evaluation Board (EVB)
+ *
+ * Copyright (C) 2022 Nuvoton Technology Corp.
+ */
+
+/dts-v1/;
+#include "ma35d1.dtsi"
+
+/ {
+ model = "Nuvoton MA35D1-EVB";
+ compatible = "nuvoton,ma35d1-evb", "nuvoton,ma35d1";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x10000000>;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
new file mode 100644
index 000000000000..7212f8de6906
--- /dev/null
+++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+
+/ {
+ compatible = "nuvoton,ma35d1";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ hxt_24m: hxt_24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "HXT_24MHz";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <12000000>;
+ };
+
+ sys: system-controller@40460000 {
+ compatible = "nuvoton,ma35d1-sys", "syscon", "simple-mfd";
+ reg = <0x0 0x40460000 0x0 0x400>;
+ };
+
+ reset: reset-controller {
+ compatible = "nuvoton,ma35d1-reset";
+ nuvoton,ma35d1-sys = <&sys>;
+ #reset-cells = <1>;
+ };
+
+ clk: clock-controller@40460200 {
+ compatible = "nuvoton,ma35d1-clk";
+ reg = <0x0 0x40460200 0x0 0x100>;
+ #clock-cells = <1>;
+ clocks = <&hxt_24m>;
+ clock-names = "HXT_24MHz";
+ assigned-clocks = <&clk CAPLL>,
+ <&clk DDRPLL>,
+ <&clk APLL>,
+ <&clk EPLL>,
+ <&clk VPLL>;
+ assigned-clock-rates = <1000000000>,
+ <266000000>,
+ <180000000>,
+ <500000000>,
+ <102000000>;
+ nuvoton,clk-pll-mode = <0 1 0 0 0>;
+ };
+
+ gic: interrupt-controller@50801000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0x0 0x50801000 0x0 0x1000>,
+ <0x0 0x50802000 0x0 0x2000>,
+ <0x0 0x50804000 0x0 0x2000>,
+ <0x0 0x50806000 0x0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+};
--
2.30.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V4 4/5] arm64: Kconfig: nuvoton: Introduce CONFIG_ARCH_NUVOTON
2022-05-10 3:25 [PATCH V4 0/5] Add initial support for MA35D1 SoC Jacky Huang
` (2 preceding siblings ...)
2022-05-10 3:25 ` [PATCH V4 3/5] arm64: dts: nuvoton: Add initial support for MA35D1 Jacky Huang
@ 2022-05-10 3:25 ` Jacky Huang
2022-05-10 3:25 ` [PATCH V4 5/5] dt-bindings: arm: Add initial bindings for Nuvoton Platform Jacky Huang
2022-05-10 7:07 ` [PATCH V4 0/5] Add initial support for MA35D1 SoC Arnd Bergmann
5 siblings, 0 replies; 26+ messages in thread
From: Jacky Huang @ 2022-05-10 3:25 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-clk, linux-arm-kernel, ychuang570808
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc,
cfli0, Jacky Huang
This adds a Kconfig option to toggle support for ARMv8 based
Nuvoton SoCs.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
arch/arm64/Kconfig.platforms | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 30b123cde02c..a6a232b9bda8 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -203,6 +203,16 @@ config ARCH_MXC
This enables support for the ARMv8 based SoCs in the
NXP i.MX family.
+config ARCH_NUVOTON
+ bool "Nuvoton Platforms"
+ select PINCTRL
+ select PM
+ select GPIOLIB
+ select SOC_BUS
+ help
+ This enables support for the ARMv8 based Nuvoton SoCs such
+ as MA35D1.
+
config ARCH_QCOM
bool "Qualcomm Platforms"
select GPIOLIB
--
2.30.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V4 5/5] dt-bindings: arm: Add initial bindings for Nuvoton Platform
2022-05-10 3:25 [PATCH V4 0/5] Add initial support for MA35D1 SoC Jacky Huang
` (3 preceding siblings ...)
2022-05-10 3:25 ` [PATCH V4 4/5] arm64: Kconfig: nuvoton: Introduce CONFIG_ARCH_NUVOTON Jacky Huang
@ 2022-05-10 3:25 ` Jacky Huang
2022-05-11 15:23 ` Rob Herring
2022-05-10 7:07 ` [PATCH V4 0/5] Add initial support for MA35D1 SoC Arnd Bergmann
5 siblings, 1 reply; 26+ messages in thread
From: Jacky Huang @ 2022-05-10 3:25 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-clk, linux-arm-kernel, ychuang570808
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc,
cfli0, Jacky Huang
Add binding for ARMv8 based Nuvotn SoCs and platform boards.
Add initial bindings for MA35D1 series development boards.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
.../devicetree/bindings/arm/nuvoton.yaml | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/nuvoton.yaml
diff --git a/Documentation/devicetree/bindings/arm/nuvoton.yaml b/Documentation/devicetree/bindings/arm/nuvoton.yaml
new file mode 100644
index 000000000000..56fb5bb41d0c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/nuvoton.yaml
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/nuvoton.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton Platforms Device Tree Bindings
+
+maintainers:
+ - Jacky Huang <ychuang3@nuvoton.com>
+
+description: |
+ Boards with an ARMv8 based Nuvoton SoC shall have the following
+ properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: MA35D1 based boards
+ items:
+ - enum:
+ - nuvoton,ma35d1-evb
+ - nuvoton,ma35d1-iot
+ - nuvoton,ma35d1-som
+ - const: nuvoton,ma35d1
+
+additionalProperties: true
+...
--
2.30.2
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH V4 3/5] arm64: dts: nuvoton: Add initial support for MA35D1
2022-05-10 3:25 ` [PATCH V4 3/5] arm64: dts: nuvoton: Add initial support for MA35D1 Jacky Huang
@ 2022-05-10 7:01 ` Arnd Bergmann
2022-05-10 8:50 ` Jacky Huang
2022-05-12 14:10 ` Krzysztof Kozlowski
1 sibling, 1 reply; 26+ messages in thread
From: Arnd Bergmann @ 2022-05-10 7:01 UTC (permalink / raw)
To: Jacky Huang
Cc: Linux Kernel Mailing List, DTML, linux-clk, Linux ARM,
ychuang570808, Rob Herring, Stephen Boyd, Krzysztof Kozlowski,
Arnd Bergmann, Olof Johansson, Catalin Marinas, Will Deacon,
SoC Team, cfli0
On Tue, May 10, 2022 at 5:25 AM Jacky Huang <ychuang3@nuvoton.com> wrote:
>
> Add the initial device tree files for Nuvoton MA35D1 Soc.
>
> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
> ---
> +
> +/ {
> + model = "Nuvoton MA35D1-EVB";
> + compatible = "nuvoton,ma35d1-evb", "nuvoton,ma35d1";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
Something seems to be missing here: you set the console to the serial0
alias, but that is not defined anywhere, and the ma35d1.dtsi file does not
appear to define any UART at all. Are you still missing the driver for this?
Please add a more detailed description in the changelog text above that
explains what kind of SoC this is (maybe a link to the product web page,
if there is one), and a status of how complete the support is: which drivers
are already merged, and which ones are still being worked on?
Arnd
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 0/5] Add initial support for MA35D1 SoC
2022-05-10 3:25 [PATCH V4 0/5] Add initial support for MA35D1 SoC Jacky Huang
` (4 preceding siblings ...)
2022-05-10 3:25 ` [PATCH V4 5/5] dt-bindings: arm: Add initial bindings for Nuvoton Platform Jacky Huang
@ 2022-05-10 7:07 ` Arnd Bergmann
2022-05-10 8:40 ` Jacky Huang
2022-05-12 14:11 ` Krzysztof Kozlowski
5 siblings, 2 replies; 26+ messages in thread
From: Arnd Bergmann @ 2022-05-10 7:07 UTC (permalink / raw)
To: Jacky Huang
Cc: Linux Kernel Mailing List, DTML, linux-clk, Linux ARM,
ychuang570808, Rob Herring, Stephen Boyd, Krzysztof Kozlowski,
Arnd Bergmann, Olof Johansson, Catalin Marinas, Will Deacon,
SoC Team, cfli0
On Tue, May 10, 2022 at 5:25 AM Jacky Huang <ychuang3@nuvoton.com> wrote:
>
> This patch series adds initial support for Nuvoton MA35D1 SoC,
> include initial dts and clock controller binding.
>
This looks fine in principle, but we are getting close to the merge window and
should finalize this quickly to make it into v5.19. I see that you don't have a
console device, as commented in the .dts patch. Normally I prefer merging
platforms only when there is at least rudimentary support for booting into
an initramfs with a serial console, but this is a flexible rule.
As with the changelog text for the .dts file, please explain in the [PATCH 0/5]
cover letter what the status is.
Regarding continued maintainership, we should discuss how you plan to
maintain this platform. In particular, there should be an entry in the
MAINTAINERS
file for the platform, either pointing to yourself, or adding it to the NPCM or
WPCM450 entries if this chip is in the same family. Is this also a BMC
implementation, or is it something different?
Arnd
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 0/5] Add initial support for MA35D1 SoC
2022-05-10 7:07 ` [PATCH V4 0/5] Add initial support for MA35D1 SoC Arnd Bergmann
@ 2022-05-10 8:40 ` Jacky Huang
2022-05-10 12:45 ` Arnd Bergmann
2022-05-12 14:11 ` Krzysztof Kozlowski
1 sibling, 1 reply; 26+ messages in thread
From: Jacky Huang @ 2022-05-10 8:40 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Linux Kernel Mailing List, DTML, linux-clk, Linux ARM,
ychuang570808, Rob Herring, Stephen Boyd, Krzysztof Kozlowski,
Olof Johansson, Catalin Marinas, Will Deacon, SoC Team, cfli0
On 2022/5/10 下午 03:07, Arnd Bergmann wrote:
> On Tue, May 10, 2022 at 5:25 AM Jacky Huang <ychuang3@nuvoton.com> wrote:
>> This patch series adds initial support for Nuvoton MA35D1 SoC,
>> include initial dts and clock controller binding.
>>
> This looks fine in principle, but we are getting close to the merge window and
> should finalize this quickly to make it into v5.19. I see that you don't have a
> console device, as commented in the .dts patch. Normally I prefer merging
> platforms only when there is at least rudimentary support for booting into
> an initramfs with a serial console, but this is a flexible rule.
>
> As with the changelog text for the .dts file, please explain in the [PATCH 0/5]
> cover letter what the status is.
>
> Regarding continued maintainership, we should discuss how you plan to
> maintain this platform. In particular, there should be an entry in the
> MAINTAINERS
> file for the platform, either pointing to yourself, or adding it to the NPCM or
> WPCM450 entries if this chip is in the same family. Is this also a BMC
> implementation, or is it something different?
>
> Arnd
Hi Arnd,
Thanks for your review.
MA35D1 is target at consumer application, while NPCM is for BMC.
MA35D1 is equipped with ARM Coretx-A35 dual-core with the M4 co-processor.
Our team has developed Linux application on MA35D1 test chip in the last
year, and
the mass production version is wafer-out in last month. It will be
announced soon.
We have ported TF-A, U-Boot, OP-TEE, and Linux 5.4.y to MA35D1 platform, and
have provided Yocto and Buildroot distribution for beta site evaluation.
All the source
code can be found at https://github.com/OpenNuvoton/MPU-Family, include the
Linux 5.4.y porting on MA35D1 platform.
Yes, we have console device driver ready. Please refer to
https://github.com/OpenNuvoton/MA35D1_linux-5.4.y/blob/master/drivers/tty/serial/ma35d1_serial.c.
But I think we have to fix coding style and have more review on it. Is
the console driver
must for the initial support submit, or can we submit it later?
And thank you to remind us to create an entry in MAINTAINERS file. I
will add
the patch in the next version.
Sincerely,
Jacky Huang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 3/5] arm64: dts: nuvoton: Add initial support for MA35D1
2022-05-10 7:01 ` Arnd Bergmann
@ 2022-05-10 8:50 ` Jacky Huang
0 siblings, 0 replies; 26+ messages in thread
From: Jacky Huang @ 2022-05-10 8:50 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Linux Kernel Mailing List, DTML, linux-clk, Linux ARM,
ychuang570808, Rob Herring, Stephen Boyd, Krzysztof Kozlowski,
Olof Johansson, Catalin Marinas, Will Deacon, SoC Team, cfli0
On 2022/5/10 下午 03:01, Arnd Bergmann wrote:
> On Tue, May 10, 2022 at 5:25 AM Jacky Huang <ychuang3@nuvoton.com> wrote:
>> Add the initial device tree files for Nuvoton MA35D1 Soc.
>>
>> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
>> ---
>> +
>> +/ {
>> + model = "Nuvoton MA35D1-EVB";
>> + compatible = "nuvoton,ma35d1-evb", "nuvoton,ma35d1";
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
> Something seems to be missing here: you set the console to the serial0
> alias, but that is not defined anywhere, and the ma35d1.dtsi file does not
> appear to define any UART at all. Are you still missing the driver for this?
>
> Please add a more detailed description in the changelog text above that
> explains what kind of SoC this is (maybe a link to the product web page,
> if there is one), and a status of how complete the support is: which drivers
> are already merged, and which ones are still being worked on?
>
> Arnd
Hi Arnd,
The serial driver is ready
(https://github.com/OpenNuvoton/MA35D1_linux-5.4.y/blob/master/drivers/tty/serial/ma35d1_serial.c),
but we have to review the coding style and porting it from Linux 5.4.y
to 5.18.
In the next patch version, I will added a brief introduction about
MA35D1 in the cover-letter [PATCH 0/5].
Thanks for your review.
Sincerely,
Jacky Huang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 0/5] Add initial support for MA35D1 SoC
2022-05-10 8:40 ` Jacky Huang
@ 2022-05-10 12:45 ` Arnd Bergmann
2022-05-11 2:31 ` Jacky Huang
0 siblings, 1 reply; 26+ messages in thread
From: Arnd Bergmann @ 2022-05-10 12:45 UTC (permalink / raw)
To: Jacky Huang
Cc: Arnd Bergmann, Linux Kernel Mailing List, DTML, linux-clk,
Linux ARM, ychuang570808, Rob Herring, Stephen Boyd,
Krzysztof Kozlowski, Olof Johansson, Catalin Marinas,
Will Deacon, SoC Team, cfli0
On Tue, May 10, 2022 at 10:40 AM Jacky Huang <ychuang3@nuvoton.com> wrote:
> On 2022/5/10 下午 03:07, Arnd Bergmann wrote:
>
> MA35D1 is target at consumer application, while NPCM is for BMC.
> MA35D1 is equipped with ARM Coretx-A35 dual-core with the M4 co-processor.
>
> Our team has developed Linux application on MA35D1 test chip in the last
> year, and
> the mass production version is wafer-out in last month. It will be
> announced soon.
>
> We have ported TF-A, U-Boot, OP-TEE, and Linux 5.4.y to MA35D1 platform, and
> have provided Yocto and Buildroot distribution for beta site evaluation.
> All the source
> code can be found at https://github.com/OpenNuvoton/MPU-Family, include the
> Linux 5.4.y porting on MA35D1 platform.
Ok, thanks for the information, this is exactly what we need in the
changelog text for the platform, and (if you send a pull request)
in the tag description.
> Yes, we have console device driver ready. Please refer to
> https://github.com/OpenNuvoton/MA35D1_linux-5.4.y/blob/master/drivers/tty/serial/ma35d1_serial.c.
> But I think we have to fix coding style and have more review on it. Is
> the console driver must for the initial support submit, or can we submit it later?
I would prefer to have it included, but it looks like this has never been
reviewed, and I can immediately see a few things that need changes
before it can get included, so I suppose we could merge the platform
without it.
The reason I'd like to have it included is that without any I/O devices
it is obvious that the code you are sending has never been tested
on the kernel version you are sending it against, and that makes it
more likely that there are bugs.
If the platform for some reason does not make it into v5.19, I would
ask you to include the serial driver in the series so we can merge
a working initial branch for v5.20.
In the meantime, please post the driver for review to the linux-kernel
and linux-serial lists by itself, and keep me on Cc.
> And thank you to remind us to create an entry in MAINTAINERS file. I
> will add the patch in the next version.
Ok.
Arnd
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 0/5] Add initial support for MA35D1 SoC
2022-05-10 12:45 ` Arnd Bergmann
@ 2022-05-11 2:31 ` Jacky Huang
0 siblings, 0 replies; 26+ messages in thread
From: Jacky Huang @ 2022-05-11 2:31 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Linux Kernel Mailing List, DTML, linux-clk, Linux ARM,
ychuang570808, Rob Herring, Stephen Boyd, Krzysztof Kozlowski,
Olof Johansson, Catalin Marinas, Will Deacon, SoC Team, cfli0
On 2022/5/10 下午 08:45, Arnd Bergmann wrote:
> On Tue, May 10, 2022 at 10:40 AM Jacky Huang <ychuang3@nuvoton.com> wrote:
>> On 2022/5/10 下午 03:07, Arnd Bergmann wrote:
>>
>> MA35D1 is target at consumer application, while NPCM is for BMC.
>> MA35D1 is equipped with ARM Coretx-A35 dual-core with the M4 co-processor.
>>
>> Our team has developed Linux application on MA35D1 test chip in the last
>> year, and
>> the mass production version is wafer-out in last month. It will be
>> announced soon.
>>
>> We have ported TF-A, U-Boot, OP-TEE, and Linux 5.4.y to MA35D1 platform, and
>> have provided Yocto and Buildroot distribution for beta site evaluation.
>> All the source
>> code can be found at https://apc01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2FOpenNuvoton%2FMPU-Family&data=05%7C01%7Cychuang3%40nuvoton.com%7Cf65d464391574dcf60af08da3282f453%7Ca3f24931d4034b4a94f17d83ac638e07%7C0%7C0%7C637877835284415849%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=b6sopMTwT8XT%2FR76qASvOtqw7zs9Kcp7lIxDw4O9%2FT8%3D&reserved=0, include the
>> Linux 5.4.y porting on MA35D1 platform.
> Ok, thanks for the information, this is exactly what we need in the
> changelog text for the platform, and (if you send a pull request)
> in the tag description.
>
>> Yes, we have console device driver ready. Please refer to
>> https://apc01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2FOpenNuvoton%2FMA35D1_linux-5.4.y%2Fblob%2Fmaster%2Fdrivers%2Ftty%2Fserial%2Fma35d1_serial.c&data=05%7C01%7Cychuang3%40nuvoton.com%7Cf65d464391574dcf60af08da3282f453%7Ca3f24931d4034b4a94f17d83ac638e07%7C0%7C0%7C637877835284415849%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=ULfLkju2X98pXn%2BeCWGrvEgRchIAlv%2FSECx%2BoJzSdWI%3D&reserved=0.
>> But I think we have to fix coding style and have more review on it. Is
>> the console driver must for the initial support submit, or can we submit it later?
> I would prefer to have it included, but it looks like this has never been
> reviewed, and I can immediately see a few things that need changes
> before it can get included, so I suppose we could merge the platform
> without it.
>
> The reason I'd like to have it included is that without any I/O devices
> it is obvious that the code you are sending has never been tested
> on the kernel version you are sending it against, and that makes it
> more likely that there are bugs.
>
> If the platform for some reason does not make it into v5.19, I would
> ask you to include the serial driver in the series so we can merge
> a working initial branch for v5.20.
>
> In the meantime, please post the driver for review to the linux-kernel
> and linux-serial lists by itself, and keep me on Cc.
>
>> And thank you to remind us to create an entry in MAINTAINERS file. I
>> will add the patch in the next version.
> Ok.
>
> Arnd
Hi Anrd,
Thanks for your kind help.
Sure, we will have review on the serial driver and include the serial
driver in the next submit.
Best Regards,
Jacky Huang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 5/5] dt-bindings: arm: Add initial bindings for Nuvoton Platform
2022-05-10 3:25 ` [PATCH V4 5/5] dt-bindings: arm: Add initial bindings for Nuvoton Platform Jacky Huang
@ 2022-05-11 15:23 ` Rob Herring
0 siblings, 0 replies; 26+ messages in thread
From: Rob Herring @ 2022-05-11 15:23 UTC (permalink / raw)
To: Jacky Huang
Cc: linux-kernel, ychuang570808, cfli0, devicetree, soc,
linux-arm-kernel, linux-clk, catalin.marinas, sboyd, robh+dt,
arnd, krzk+dt, will, olof
On Tue, 10 May 2022 11:25:58 +0800, Jacky Huang wrote:
> Add binding for ARMv8 based Nuvotn SoCs and platform boards.
> Add initial bindings for MA35D1 series development boards.
>
> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
> ---
> .../devicetree/bindings/arm/nuvoton.yaml | 31 +++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/nuvoton.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 2/5] dt-bindings: clock: Document MA35D1 clock controller bindings
2022-05-10 3:25 ` [PATCH V4 2/5] dt-bindings: clock: Document MA35D1 clock controller bindings Jacky Huang
@ 2022-05-12 14:04 ` Krzysztof Kozlowski
2022-05-13 6:25 ` Jacky Huang
0 siblings, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-12 14:04 UTC (permalink / raw)
To: Jacky Huang, linux-kernel, devicetree, linux-clk,
linux-arm-kernel, ychuang570808
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc, cfli0
On 10/05/2022 05:25, Jacky Huang wrote:
> Add documentation to describe Nuvoton MA35D1 clock driver bindings.
>
> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
> +
> + clk: clock-controller@40460200 {
> + compatible = "nuvoton,ma35d1-clk";
> + reg = <0x0 0x40460200 0x0 0x100>;
I don't think you tested your bindings. This fails.
clock-names below as well. Please do not send untested code.
Testing is explained here:
https://elixir.bootlin.com/linux/v5.18-rc6/source/Documentation/devicetree/bindings/writing-schema.rst#L111
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 3/5] arm64: dts: nuvoton: Add initial support for MA35D1
2022-05-10 3:25 ` [PATCH V4 3/5] arm64: dts: nuvoton: Add initial support for MA35D1 Jacky Huang
2022-05-10 7:01 ` Arnd Bergmann
@ 2022-05-12 14:10 ` Krzysztof Kozlowski
2022-05-13 6:48 ` Jacky Huang
1 sibling, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-12 14:10 UTC (permalink / raw)
To: Jacky Huang, linux-kernel, devicetree, linux-clk,
linux-arm-kernel, ychuang570808
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc, cfli0
On 10/05/2022 05:25, Jacky Huang wrote:
> Add the initial device tree files for Nuvoton MA35D1 Soc.
>
> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/nuvoton/Makefile | 2 +
> arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts | 24 +++++
> arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 120 +++++++++++++++++++++
> 4 files changed, 147 insertions(+)
> create mode 100644 arch/arm64/boot/dts/nuvoton/Makefile
> create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts
> create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 1ba04e31a438..7b107fa7414b 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -19,6 +19,7 @@ subdir-y += lg
> subdir-y += marvell
> subdir-y += mediatek
> subdir-y += microchip
> +subdir-y += nuvoton
> subdir-y += nvidia
> subdir-y += qcom
> subdir-y += realtek
> diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile
> new file mode 100644
> index 000000000000..e1e0c466bf5e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nuvoton/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_NUVOTON) += ma35d1-evb.dtb
> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts
> new file mode 100644
> index 000000000000..95f0facb0476
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for MA35D1 Evaluation Board (EVB)
> + *
> + * Copyright (C) 2022 Nuvoton Technology Corp.
> + */
> +
> +/dts-v1/;
> +#include "ma35d1.dtsi"
> +
> +/ {
> + model = "Nuvoton MA35D1-EVB";
> + compatible = "nuvoton,ma35d1-evb", "nuvoton,ma35d1";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x0 0x10000000>;
> + };
> +};
> +
.git/rebase-apply/patch:60: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
> new file mode 100644
> index 000000000000..7212f8de6906
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
> @@ -0,0 +1,120 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Copyright (c) 2022 Nuvoton Technology Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
> +
> +/ {
> + compatible = "nuvoton,ma35d1";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a35";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a35";
> + reg = <0x1>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + L2_0: l2-cache0 {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + hxt_24m: hxt_24mhz {
No underscores in node name. Generic node names, so "clock-X" or
"clock-some-suffix"
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
This does not look like property of SoC. Where is this clock defined? In
the SoC or on the board?
> + clock-output-names = "HXT_24MHz";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <12000000>;
> + };
> +
> + sys: system-controller@40460000 {
> + compatible = "nuvoton,ma35d1-sys", "syscon", "simple-mfd";
Why is this a simple-mfd if there are no children here? What do you want
to instantiate here?
Where is the nuvoton,ma35d1-sys compatible documented?
> + reg = <0x0 0x40460000 0x0 0x400>;
> + };
> +
> + reset: reset-controller {
> + compatible = "nuvoton,ma35d1-reset";
Also not documented.
> + nuvoton,ma35d1-sys = <&sys>;
> + #reset-cells = <1>;
> + };
> +
> + clk: clock-controller@40460200 {
> + compatible = "nuvoton,ma35d1-clk";
> + reg = <0x0 0x40460200 0x0 0x100>;
> + #clock-cells = <1>;
> + clocks = <&hxt_24m>;
> + clock-names = "HXT_24MHz";
Please test your DTS with make dtbs_check.
Don't send DTS which does not pass the checks. It is unnecessary use of
reviewers time when the same job can be done by automated tools.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 0/5] Add initial support for MA35D1 SoC
2022-05-10 7:07 ` [PATCH V4 0/5] Add initial support for MA35D1 SoC Arnd Bergmann
2022-05-10 8:40 ` Jacky Huang
@ 2022-05-12 14:11 ` Krzysztof Kozlowski
2022-05-12 14:35 ` Arnd Bergmann
1 sibling, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-12 14:11 UTC (permalink / raw)
To: Arnd Bergmann, Jacky Huang
Cc: Linux Kernel Mailing List, DTML, linux-clk, Linux ARM,
ychuang570808, Rob Herring, Stephen Boyd, Krzysztof Kozlowski,
Olof Johansson, Catalin Marinas, Will Deacon, SoC Team, cfli0
On 10/05/2022 09:07, Arnd Bergmann wrote:
> On Tue, May 10, 2022 at 5:25 AM Jacky Huang <ychuang3@nuvoton.com> wrote:
>>
>> This patch series adds initial support for Nuvoton MA35D1 SoC,
>> include initial dts and clock controller binding.
>>
>
> This looks fine in principle, but we are getting close to the merge window and
> should finalize this quickly to make it into v5.19. I see that you don't have a
> console device, as commented in the .dts patch. Normally I prefer merging
> platforms only when there is at least rudimentary support for booting into
> an initramfs with a serial console, but this is a flexible rule.
I disagree. It does not look fine - does not pass `make dtbs_check` even
with Nuvoton bindings...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 0/5] Add initial support for MA35D1 SoC
2022-05-12 14:11 ` Krzysztof Kozlowski
@ 2022-05-12 14:35 ` Arnd Bergmann
2022-05-13 6:53 ` Jacky Huang
0 siblings, 1 reply; 26+ messages in thread
From: Arnd Bergmann @ 2022-05-12 14:35 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Arnd Bergmann, Jacky Huang, Linux Kernel Mailing List, DTML,
linux-clk, Linux ARM, ychuang570808, Rob Herring, Stephen Boyd,
Krzysztof Kozlowski, Olof Johansson, Catalin Marinas,
Will Deacon, SoC Team, cfli0
On Thu, May 12, 2022 at 4:11 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 10/05/2022 09:07, Arnd Bergmann wrote:
> > On Tue, May 10, 2022 at 5:25 AM Jacky Huang <ychuang3@nuvoton.com> wrote:
> >>
> >> This patch series adds initial support for Nuvoton MA35D1 SoC,
> >> include initial dts and clock controller binding.
> >>
> >
> > This looks fine in principle, but we are getting close to the merge window and
> > should finalize this quickly to make it into v5.19. I see that you don't have a
> > console device, as commented in the .dts patch. Normally I prefer merging
> > platforms only when there is at least rudimentary support for booting into
> > an initramfs with a serial console, but this is a flexible rule.
>
> I disagree. It does not look fine - does not pass `make dtbs_check` even
> with Nuvoton bindings...
Ok, thanks for taking a look. It was already late for 5.19 and missing the uart
driver, so it was clear it had not seen actual runtime testing. Let's try
aiming for 5.20 then.
Arnd
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 2/5] dt-bindings: clock: Document MA35D1 clock controller bindings
2022-05-12 14:04 ` Krzysztof Kozlowski
@ 2022-05-13 6:25 ` Jacky Huang
2022-05-13 6:54 ` Krzysztof Kozlowski
0 siblings, 1 reply; 26+ messages in thread
From: Jacky Huang @ 2022-05-13 6:25 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-kernel, devicetree, linux-clk,
linux-arm-kernel, ychuang570808
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc, cfli0
On 2022/5/12 下午 10:04, Krzysztof Kozlowski wrote:
> On 10/05/2022 05:25, Jacky Huang wrote:
>> Add documentation to describe Nuvoton MA35D1 clock driver bindings.
>>
>> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
>> +
>> + clk: clock-controller@40460200 {
>> + compatible = "nuvoton,ma35d1-clk";
>> + reg = <0x0 0x40460200 0x0 0x100>;
> I don't think you tested your bindings. This fails.
>
> clock-names below as well. Please do not send untested code.
>
> Testing is explained here:
> https://apc01.safelinks.protection.outlook.com/?url=https%3A%2F%2Felixir.bootlin.com%2Flinux%2Fv5.18-rc6%2Fsource%2FDocumentation%2Fdevicetree%2Fbindings%2Fwriting-schema.rst%23L111&data=05%7C01%7Cychuang3%40nuvoton.com%7C7f9b081f94a642e8b40b08da34204e53%7Ca3f24931d4034b4a94f17d83ac638e07%7C0%7C0%7C637879610603173566%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=kqInjscLvZpOSWtsN%2BPW3s%2BPeaK5KCD1weTH2JiHqxg%3D&reserved=0
>
> Best regards,
> Krzysztof
I run the test make DT_CHECKER_FLAGS=-m dt_binding_check, but not run
dtbs_check.
I will fix it. Thank you.
Sincerely,
Jacky Huang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 3/5] arm64: dts: nuvoton: Add initial support for MA35D1
2022-05-12 14:10 ` Krzysztof Kozlowski
@ 2022-05-13 6:48 ` Jacky Huang
2022-05-13 6:57 ` Krzysztof Kozlowski
0 siblings, 1 reply; 26+ messages in thread
From: Jacky Huang @ 2022-05-13 6:48 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-kernel, devicetree, linux-clk,
linux-arm-kernel, ychuang570808
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc, cfli0
On 2022/5/12 下午 10:10, Krzysztof Kozlowski wrote:
> On 10/05/2022 05:25, Jacky Huang wrote:
>> Add the initial device tree files for Nuvoton MA35D1 Soc.
>>
>> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
>> ---
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/nuvoton/Makefile | 2 +
>> arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts | 24 +++++
>> arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 120 +++++++++++++++++++++
>> 4 files changed, 147 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/nuvoton/Makefile
>> create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts
>> create mode 100644 arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
>> index 1ba04e31a438..7b107fa7414b 100644
>> --- a/arch/arm64/boot/dts/Makefile
>> +++ b/arch/arm64/boot/dts/Makefile
>> @@ -19,6 +19,7 @@ subdir-y += lg
>> subdir-y += marvell
>> subdir-y += mediatek
>> subdir-y += microchip
>> +subdir-y += nuvoton
>> subdir-y += nvidia
>> subdir-y += qcom
>> subdir-y += realtek
>> diff --git a/arch/arm64/boot/dts/nuvoton/Makefile b/arch/arm64/boot/dts/nuvoton/Makefile
>> new file mode 100644
>> index 000000000000..e1e0c466bf5e
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/nuvoton/Makefile
>> @@ -0,0 +1,2 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +dtb-$(CONFIG_ARCH_NUVOTON) += ma35d1-evb.dtb
>> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts
>> new file mode 100644
>> index 000000000000..95f0facb0476
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-evb.dts
>> @@ -0,0 +1,24 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +/*
>> + * Device Tree Source for MA35D1 Evaluation Board (EVB)
>> + *
>> + * Copyright (C) 2022 Nuvoton Technology Corp.
>> + */
>> +
>> +/dts-v1/;
>> +#include "ma35d1.dtsi"
>> +
>> +/ {
>> + model = "Nuvoton MA35D1-EVB";
>> + compatible = "nuvoton,ma35d1-evb", "nuvoton,ma35d1";
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + memory@80000000 {
>> + device_type = "memory";
>> + reg = <0x0 0x80000000 0x0 0x10000000>;
>> + };
>> +};
>> +
>
> .git/rebase-apply/patch:60: new blank line at EOF.
>
> +
>
> warning: 1 line adds whitespace errors.
>
I will fix it.
>
>> diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
>> new file mode 100644
>> index 000000000000..7212f8de6906
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
>> @@ -0,0 +1,120 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +/*
>> + * Copyright (c) 2022 Nuvoton Technology Corp.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
>> +
>> +/ {
>> + compatible = "nuvoton,ma35d1";
>> + interrupt-parent = <&gic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&cpu0>;
>> + };
>> + core1 {
>> + cpu = <&cpu1>;
>> + };
>> + };
>> + };
>> +
>> + cpu0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a35";
>> + reg = <0x0>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_0>;
>> + };
>> +
>> + cpu1: cpu@1 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a35";
>> + reg = <0x1>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_0>;
>> + };
>> +
>> + L2_0: l2-cache0 {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + };
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-0.2";
>> + method = "smc";
>> + };
>> +
>> + hxt_24m: hxt_24mhz {
> No underscores in node name. Generic node names, so "clock-X" or
> "clock-some-suffix"
OK, I will modify it as
hxt-24m: hxt-24mhz
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <24000000>;
> This does not look like property of SoC. Where is this clock defined? In
> the SoC or on the board?
It's an external crystal on the board.
I add this node, because it's the clock source of clock controller.
It always present on all ma35d1 boards.
clk: clock-controller@40460200 {
compatible = "nuvoton,ma35d1-clk";
reg = <0x0 0x40460200 0x0 0x100>;
#clock-cells = <1>;
clocks = <&hxt_24m>;
clock-names = "HXT_24MHz";
...
>> + clock-output-names = "HXT_24MHz";
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>> + IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
>> + IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
>> + IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
>> + IRQ_TYPE_LEVEL_LOW)>;
>> + clock-frequency = <12000000>;
>> + };
>> +
>> + sys: system-controller@40460000 {
>> + compatible = "nuvoton,ma35d1-sys", "syscon", "simple-mfd";
> Why is this a simple-mfd if there are no children here? What do you want
> to instantiate here?
It's not a device, but a set of registers for system level control.
I want to provide a register base mapping for other devices to access
system control registers.
> Where is the nuvoton,ma35d1-sys compatible documented?
OK, I will add the compatible document in next version.
>> + reg = <0x0 0x40460000 0x0 0x400>;
>> + };
>> +
>> + reset: reset-controller {
>> + compatible = "nuvoton,ma35d1-reset";
> Also not documented.
I will also add the document for it.
>
>> + nuvoton,ma35d1-sys = <&sys>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + clk: clock-controller@40460200 {
>> + compatible = "nuvoton,ma35d1-clk";
>> + reg = <0x0 0x40460200 0x0 0x100>;
>> + #clock-cells = <1>;
>> + clocks = <&hxt_24m>;
>> + clock-names = "HXT_24MHz";
> Please test your DTS with make dtbs_check.
>
> Don't send DTS which does not pass the checks. It is unnecessary use of
> reviewers time when the same job can be done by automated tools.
>
> Best regards,
> Krzysztof
Yes, I read the "writing-schema.rst" and know how to do now.
Thank you.
Sincerely,
Jacky Huang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 0/5] Add initial support for MA35D1 SoC
2022-05-12 14:35 ` Arnd Bergmann
@ 2022-05-13 6:53 ` Jacky Huang
2022-05-13 6:55 ` Krzysztof Kozlowski
0 siblings, 1 reply; 26+ messages in thread
From: Jacky Huang @ 2022-05-13 6:53 UTC (permalink / raw)
To: Arnd Bergmann, Krzysztof Kozlowski
Cc: Linux Kernel Mailing List, DTML, linux-clk, Linux ARM,
ychuang570808, Rob Herring, Stephen Boyd, Krzysztof Kozlowski,
Olof Johansson, Catalin Marinas, Will Deacon, SoC Team, cfli0
On 2022/5/12 下午 10:35, Arnd Bergmann wrote:
> On Thu, May 12, 2022 at 4:11 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 10/05/2022 09:07, Arnd Bergmann wrote:
>>> On Tue, May 10, 2022 at 5:25 AM Jacky Huang <ychuang3@nuvoton.com> wrote:
>>>> This patch series adds initial support for Nuvoton MA35D1 SoC,
>>>> include initial dts and clock controller binding.
>>>>
>>> This looks fine in principle, but we are getting close to the merge window and
>>> should finalize this quickly to make it into v5.19. I see that you don't have a
>>> console device, as commented in the .dts patch. Normally I prefer merging
>>> platforms only when there is at least rudimentary support for booting into
>>> an initramfs with a serial console, but this is a flexible rule.
>> I disagree. It does not look fine - does not pass `make dtbs_check` even
>> with Nuvoton bindings...
> Ok, thanks for taking a look. It was already late for 5.19 and missing the uart
> driver, so it was clear it had not seen actual runtime testing. Let's try
> aiming for 5.20 then.
>
> Arnd
Thanks for your review and help.
I will run the dtbs_check, add binding document, and include serial
driver in the next version.
sincerely,
Jacky Huang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 2/5] dt-bindings: clock: Document MA35D1 clock controller bindings
2022-05-13 6:25 ` Jacky Huang
@ 2022-05-13 6:54 ` Krzysztof Kozlowski
0 siblings, 0 replies; 26+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-13 6:54 UTC (permalink / raw)
To: Jacky Huang, linux-kernel, devicetree, linux-clk,
linux-arm-kernel, ychuang570808
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc, cfli0
On 13/05/2022 08:25, Jacky Huang wrote:
>
>
> On 2022/5/12 下午 10:04, Krzysztof Kozlowski wrote:
>> On 10/05/2022 05:25, Jacky Huang wrote:
>>> Add documentation to describe Nuvoton MA35D1 clock driver bindings.
>>>
>>> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
>>> +
>>> + clk: clock-controller@40460200 {
>>> + compatible = "nuvoton,ma35d1-clk";
>>> + reg = <0x0 0x40460200 0x0 0x100>;
>> I don't think you tested your bindings. This fails.
>>
>> clock-names below as well. Please do not send untested code.
>>
>> Testing is explained here:
>> https://apc01.safelinks.protection.outlook.com/?url=https%3A%2F%2Felixir.bootlin.com%2Flinux%2Fv5.18-rc6%2Fsource%2FDocumentation%2Fdevicetree%2Fbindings%2Fwriting-schema.rst%23L111&data=05%7C01%7Cychuang3%40nuvoton.com%7C7f9b081f94a642e8b40b08da34204e53%7Ca3f24931d4034b4a94f17d83ac638e07%7C0%7C0%7C637879610603173566%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=kqInjscLvZpOSWtsN%2BPW3s%2BPeaK5KCD1weTH2JiHqxg%3D&reserved=0
>>
>> Best regards,
>> Krzysztof
>
> I run the test make DT_CHECKER_FLAGS=-m dt_binding_check, but not run
> dtbs_check.
It is the `make dt_binding_check` which fails here, so what do you mean
that you run it? It cannot pass, the code is clearly not correct.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 0/5] Add initial support for MA35D1 SoC
2022-05-13 6:53 ` Jacky Huang
@ 2022-05-13 6:55 ` Krzysztof Kozlowski
2022-05-13 7:00 ` Jacky Huang
0 siblings, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-13 6:55 UTC (permalink / raw)
To: Jacky Huang, Arnd Bergmann
Cc: Linux Kernel Mailing List, DTML, linux-clk, Linux ARM,
ychuang570808, Rob Herring, Stephen Boyd, Krzysztof Kozlowski,
Olof Johansson, Catalin Marinas, Will Deacon, SoC Team, cfli0
On 13/05/2022 08:53, Jacky Huang wrote:
>
> Thanks for your review and help.
> I will run the dtbs_check, add binding document, and include serial
> driver in the next version.
Except dtbs_check you have to run dt_binding_check because this is the
one which was failing at the first place.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 3/5] arm64: dts: nuvoton: Add initial support for MA35D1
2022-05-13 6:48 ` Jacky Huang
@ 2022-05-13 6:57 ` Krzysztof Kozlowski
2022-05-15 5:53 ` Jacky Huang
0 siblings, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-13 6:57 UTC (permalink / raw)
To: Jacky Huang, linux-kernel, devicetree, linux-clk,
linux-arm-kernel, ychuang570808
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc, cfli0
On 13/05/2022 08:48, Jacky Huang wrote:
>>> +
>>> + hxt_24m: hxt_24mhz {
>> No underscores in node name. Generic node names, so "clock-X" or
>> "clock-some-suffix"
>
> OK, I will modify it as
> hxt-24m: hxt-24mhz
No, it is not a generic node name. Please read my reply again.
>
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <24000000>;
>> This does not look like property of SoC. Where is this clock defined? In
>> the SoC or on the board?
>
> It's an external crystal on the board.
> I add this node, because it's the clock source of clock controller.
> It always present on all ma35d1 boards.
>
> clk: clock-controller@40460200 {
> compatible = "nuvoton,ma35d1-clk";
> reg = <0x0 0x40460200 0x0 0x100>;
> #clock-cells = <1>;
> clocks = <&hxt_24m>;
> clock-names = "HXT_24MHz";
> ...
>
>>> + clock-output-names = "HXT_24MHz";
>>> + };
>>> +
>>> + timer {
>>> + compatible = "arm,armv8-timer";
>>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>>> + IRQ_TYPE_LEVEL_LOW)>,
>>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
>>> + IRQ_TYPE_LEVEL_LOW)>,
>>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
>>> + IRQ_TYPE_LEVEL_LOW)>,
>>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
>>> + IRQ_TYPE_LEVEL_LOW)>;
>>> + clock-frequency = <12000000>;
>>> + };
>>> +
>>> + sys: system-controller@40460000 {
>>> + compatible = "nuvoton,ma35d1-sys", "syscon", "simple-mfd";
>> Why is this a simple-mfd if there are no children here? What do you want
>> to instantiate here?
>
> It's not a device, but a set of registers for system level control.
> I want to provide a register base mapping for other devices to access
> system control registers.
This does not explain why you need simple-mfd. simple-mfd is not for
providing a register base mapping for other devices.
>
>> Where is the nuvoton,ma35d1-sys compatible documented?
>
> OK, I will add the compatible document in next version.
>
>
>>> + reg = <0x0 0x40460000 0x0 0x400>;
>>> + };
>>> +
>>> + reset: reset-controller {
>>> + compatible = "nuvoton,ma35d1-reset";
>> Also not documented.
>
> I will also add the document for it.
All of these should fail on checkpatch which points that you either did
not run it or ignored the result.
Please run checkpatch on all your submissions to Linux kernel and be
sure that there is no warning or error.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 0/5] Add initial support for MA35D1 SoC
2022-05-13 6:55 ` Krzysztof Kozlowski
@ 2022-05-13 7:00 ` Jacky Huang
0 siblings, 0 replies; 26+ messages in thread
From: Jacky Huang @ 2022-05-13 7:00 UTC (permalink / raw)
To: Krzysztof Kozlowski, Arnd Bergmann
Cc: Linux Kernel Mailing List, DTML, linux-clk, Linux ARM,
ychuang570808, Rob Herring, Stephen Boyd, Krzysztof Kozlowski,
Olof Johansson, Catalin Marinas, Will Deacon, SoC Team, cfli0
On 2022/5/13 下午 02:55, Krzysztof Kozlowski wrote:
> On 13/05/2022 08:53, Jacky Huang wrote:
>> Thanks for your review and help.
>> I will run the dtbs_check, add binding document, and include serial
>> driver in the next version.
> Except dtbs_check you have to run dt_binding_check because this is the
> one which was failing at the first place.
>
> Best regards,
> Krzysztof
OK, I got it. Thank you very much.
Sincerely,
Jacky Huang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 3/5] arm64: dts: nuvoton: Add initial support for MA35D1
2022-05-13 6:57 ` Krzysztof Kozlowski
@ 2022-05-15 5:53 ` Jacky Huang
2022-05-15 9:54 ` Krzysztof Kozlowski
0 siblings, 1 reply; 26+ messages in thread
From: Jacky Huang @ 2022-05-15 5:53 UTC (permalink / raw)
To: Krzysztof Kozlowski, Jacky Huang, linux-kernel, devicetree,
linux-clk, linux-arm-kernel
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc, cfli0
On 2022/5/13 下午 02:57, Krzysztof Kozlowski wrote:
> On 13/05/2022 08:48, Jacky Huang wrote:
>>>> +
>>>> + hxt_24m: hxt_24mhz {
>>> No underscores in node name. Generic node names, so "clock-X" or
>>> "clock-some-suffix"
>> OK, I will modify it as
>> hxt-24m: hxt-24mhz
> No, it is not a generic node name. Please read my reply again.
I would modify it as
clock-hxt: clock-hspd-ext-crystal
>
>>>> + compatible = "fixed-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <24000000>;
>>> This does not look like property of SoC. Where is this clock defined? In
>>> the SoC or on the board?
>> It's an external crystal on the board.
>> I add this node, because it's the clock source of clock controller.
>> It always present on all ma35d1 boards.
>>
>> clk: clock-controller@40460200 {
>> compatible = "nuvoton,ma35d1-clk";
>> reg = <0x0 0x40460200 0x0 0x100>;
>> #clock-cells = <1>;
>> clocks = <&hxt_24m>;
>> clock-names = "HXT_24MHz";
>> ...
>>
>>>> + clock-output-names = "HXT_24MHz";
>>>> + };
>>>> +
>>>> + timer {
>>>> + compatible = "arm,armv8-timer";
>>>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>>>> + IRQ_TYPE_LEVEL_LOW)>,
>>>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
>>>> + IRQ_TYPE_LEVEL_LOW)>,
>>>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
>>>> + IRQ_TYPE_LEVEL_LOW)>,
>>>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
>>>> + IRQ_TYPE_LEVEL_LOW)>;
>>>> + clock-frequency = <12000000>;
>>>> + };
>>>> +
>>>> + sys: system-controller@40460000 {
>>>> + compatible = "nuvoton,ma35d1-sys", "syscon", "simple-mfd";
>>> Why is this a simple-mfd if there are no children here? What do you want
>>> to instantiate here?
>> It's not a device, but a set of registers for system level control.
>> I want to provide a register base mapping for other devices to access
>> system control registers.
> This does not explain why you need simple-mfd. simple-mfd is not for
> providing a register base mapping for other devices.
OK, I will remove the "simple-mfd" from sys node.
>>> Where is the nuvoton,ma35d1-sys compatible documented?
>> OK, I will add the compatible document in next version.
>>
>>
>>>> + reg = <0x0 0x40460000 0x0 0x400>;
>>>> + };
>>>> +
>>>> + reset: reset-controller {
>>>> + compatible = "nuvoton,ma35d1-reset";
>>> Also not documented.
>> I will also add the document for it.
> All of these should fail on checkpatch which points that you either did
> not run it or ignored the result.
>
> Please run checkpatch on all your submissions to Linux kernel and be
> sure that there is no warning or error.
>
>
>
> Best regards,
> Krzysztof
Sure, thank you for reminding.
Sincerely,.
Jacky Huang
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 3/5] arm64: dts: nuvoton: Add initial support for MA35D1
2022-05-15 5:53 ` Jacky Huang
@ 2022-05-15 9:54 ` Krzysztof Kozlowski
0 siblings, 0 replies; 26+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-15 9:54 UTC (permalink / raw)
To: Jacky Huang, Jacky Huang, linux-kernel, devicetree, linux-clk,
linux-arm-kernel
Cc: robh+dt, sboyd, krzk+dt, arnd, olof, catalin.marinas, will, soc, cfli0
On 15/05/2022 07:53, Jacky Huang wrote:
>
> On 2022/5/13 下午 02:57, Krzysztof Kozlowski wrote:
>> On 13/05/2022 08:48, Jacky Huang wrote:
>>>>> +
>>>>> + hxt_24m: hxt_24mhz {
>>>> No underscores in node name. Generic node names, so "clock-X" or
>>>> "clock-some-suffix"
>>> OK, I will modify it as
>>> hxt-24m: hxt-24mhz
>> No, it is not a generic node name. Please read my reply again.
>
> I would modify it as
>
> clock-hxt: clock-hspd-ext-crystal
>
>
>>
>>>>> + compatible = "fixed-clock";
>>>>> + #clock-cells = <0>;
>>>>> + clock-frequency = <24000000>;
>>>> This does not look like property of SoC. Where is this clock defined? In
>>>> the SoC or on the board?
>>> It's an external crystal on the board.
>>> I add this node, because it's the clock source of clock controller.
>>> It always present on all ma35d1 boards.
>>>
Then such clock is not a property of a SoC, but a board. Feel free to
simplify DTS by storing most of the clock node in DTSI, but frequency
should be defined by each board.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2022-05-15 9:54 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-10 3:25 [PATCH V4 0/5] Add initial support for MA35D1 SoC Jacky Huang
2022-05-10 3:25 ` [PATCH V4 1/5] dt-bindings: clock: add binding for MA35D1 clock controller Jacky Huang
2022-05-10 3:25 ` [PATCH V4 2/5] dt-bindings: clock: Document MA35D1 clock controller bindings Jacky Huang
2022-05-12 14:04 ` Krzysztof Kozlowski
2022-05-13 6:25 ` Jacky Huang
2022-05-13 6:54 ` Krzysztof Kozlowski
2022-05-10 3:25 ` [PATCH V4 3/5] arm64: dts: nuvoton: Add initial support for MA35D1 Jacky Huang
2022-05-10 7:01 ` Arnd Bergmann
2022-05-10 8:50 ` Jacky Huang
2022-05-12 14:10 ` Krzysztof Kozlowski
2022-05-13 6:48 ` Jacky Huang
2022-05-13 6:57 ` Krzysztof Kozlowski
2022-05-15 5:53 ` Jacky Huang
2022-05-15 9:54 ` Krzysztof Kozlowski
2022-05-10 3:25 ` [PATCH V4 4/5] arm64: Kconfig: nuvoton: Introduce CONFIG_ARCH_NUVOTON Jacky Huang
2022-05-10 3:25 ` [PATCH V4 5/5] dt-bindings: arm: Add initial bindings for Nuvoton Platform Jacky Huang
2022-05-11 15:23 ` Rob Herring
2022-05-10 7:07 ` [PATCH V4 0/5] Add initial support for MA35D1 SoC Arnd Bergmann
2022-05-10 8:40 ` Jacky Huang
2022-05-10 12:45 ` Arnd Bergmann
2022-05-11 2:31 ` Jacky Huang
2022-05-12 14:11 ` Krzysztof Kozlowski
2022-05-12 14:35 ` Arnd Bergmann
2022-05-13 6:53 ` Jacky Huang
2022-05-13 6:55 ` Krzysztof Kozlowski
2022-05-13 7:00 ` Jacky Huang
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