From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF06BC4332F for ; Thu, 12 May 2022 00:06:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349560AbiELAGB (ORCPT ); Wed, 11 May 2022 20:06:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349552AbiELAFz (ORCPT ); Wed, 11 May 2022 20:05:55 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60CEC13F1F for ; Wed, 11 May 2022 17:05:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652313954; x=1683849954; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=iEGg3ZUCdx9uygbP/iQOaVPDEP0BAuMfZKqEQ1Cahnc=; b=dnMGvaTXHWuuTExgra1KNQ/YaJWLXwDZY3IY2u2jTWDTSwzW0QOt+n9X BuEEi3WZFEjOC/IyS9LoxDKm7dXgawfOGoW/q3SpaJpppFIk7aElieQQK bAOOJgYlNPju5LEYICGrGMSHkYW411W0r5YR0lRIihzSKoSBTAr2/Eqij 76UIGnXl6+ousI702WdCErVxQPHfcncu6etVxZW+E1CtKSWA0EiU3AC2p 3a7EwE0C4bHrX5yXaP/B1KLHobxDi82IlpEhQ+7udj1rLpI/O2BLfCLd5 VEj6O8yRAswmaWI8WFVlYLVi4M57ugSw3PVPxsqZwAWTmrsGdFRPNMmOt w==; X-IronPort-AV: E=McAfee;i="6400,9594,10344"; a="330448449" X-IronPort-AV: E=Sophos;i="5.91,218,1647327600"; d="scan'208";a="330448449" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 17:05:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,218,1647327600"; d="scan'208";a="658374063" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by FMSMGA003.fm.intel.com with ESMTP; 11 May 2022 17:05:53 -0700 Date: Wed, 11 May 2022 17:09:24 -0700 From: Ricardo Neri To: Thomas Gleixner Cc: x86@kernel.org, Tony Luck , Andi Kleen , Stephane Eranian , Andrew Morton , Joerg Roedel , Suravee Suthikulpanit , David Woodhouse , Lu Baolu , Nicholas Piggin , "Ravi V. Shankar" , Ricardo Neri , iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 01/29] irq/matrix: Expose functions to allocate the best CPU for new vectors Message-ID: <20220512000924.GA16273@ranerica-svr.sc.intel.com> References: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com> <20220506000008.30892-2-ricardo.neri-calderon@linux.intel.com> <878rreh27n.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <878rreh27n.ffs@tglx> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, May 06, 2022 at 09:48:28PM +0200, Thomas Gleixner wrote: > Ricardo, Thank you very much for your feedback Thomas! I am sorry for my late reply, I had been out of office. > > On Thu, May 05 2022 at 16:59, Ricardo Neri wrote: > > Certain types of interrupts, such as NMI, do not have an associated vector. > > They, however, target specific CPUs. Thus, when assigning the destination > > CPU, it is beneficial to select the one with the lowest number of > > vectors. > > Why is that beneficial especially in the context of a NMI watchdog which > then broadcasts the NMI to all other CPUs? My intent was not the NMI watchdog specifically but potential use cases that do not involve NMI broadcasts. If the NMI targets a single CPU, it is best to select the CPU with the lowest vector allocation count. > > That's wishful thinking perhaps, but I don't see any benefit at all. > > > Prepend the functions matrix_find_best_cpu_managed() and > > matrix_find_best_cpu_managed() > > The same function prepended twice becomes two functions :) > Sorry, I missed this. > > with the irq_ prefix and expose them for > > IRQ controllers to use when allocating and activating vector-less IRQs. > > There is no such thing like a vectorless IRQ. NMIs have a vector. Can we > please describe facts and not pulled out of thin air concepts which do > not exist? Thank you for the clarification. I see your point. I wrote this patch because maskable interrupts and NMIs have different entry points. As you state, however, the also have a vector. I can drop this patch. BR, Ricardo > > Thanks, > > tglx