From: Stafford Horne <shorne@gmail.com>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Openrisc <openrisc@lists.librecores.org>,
Stafford Horne <shorne@gmail.com>,
Jonas Bonn <jonas@southpole.se>,
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Subject: [PATCH 01/13] openrisc: Add gcc machine instruction flag configuration
Date: Sun, 15 May 2022 21:41:46 +0900 [thread overview]
Message-ID: <20220515124158.3167452-2-shorne@gmail.com> (raw)
In-Reply-To: <20220515124158.3167452-1-shorne@gmail.com>
OpenRISC GCC supports flags to enable the backend to output instructions
if they are supported by a target processor. This patch adds
configuration flags to enable configuring these flags to tune the kernel
for a particular CPU configuration.
In the future we could also enable all of these flags by default and
provide instruction emulation in the kernel to make these choices easier
for users but this is what we provide for now.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/Kconfig | 53 ++++++++++++++++++++++++++++++++++++++++++
arch/openrisc/Makefile | 17 ++++++++++++++
2 files changed, 70 insertions(+)
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 0d68adf6e02b..ea7eac20911a 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -114,6 +114,59 @@ config OPENRISC_HAVE_INST_DIV
default y
help
Select this if your implementation has a hardware divide instruction
+
+config OPENRISC_HAVE_INST_CMOV
+ bool "Have instruction l.cmov for conditional move"
+ default y
+ help
+ This config enables gcc to generate l.cmov instructions when compiling
+ the kernel which in general will improve performance and reduce the
+ binary size.
+
+ Select this if your implementation has support for the Class II
+ l.cmov conistional move instruction.
+
+ Say N if you are unsure.
+
+config OPENRISC_HAVE_INST_ROR
+ bool "Have instruction l.ror for rotate right"
+ default y
+ help
+ This config enables gcc to generate l.ror instructions when compiling
+ the kernel which in general will improve performance and reduce the
+ binary size.
+
+ Select this if your implementation has support for the Class II
+ l.ror rotate right instruction.
+
+ Say N if you are unsure.
+
+config OPENRISC_HAVE_INST_RORI
+ bool "Have instruction l.rori for rotate right with immediate"
+ default y
+ help
+ This config enables gcc to generate l.rori instructions when compiling
+ the kernel which in general will improve performance and reduce the
+ binary size.
+
+ Select this if your implementation has support for the Class II
+ l.rori rotate right with immediate instruction.
+
+ Say N if you are unsure.
+
+config OPENRISC_HAVE_INST_SEXT
+ bool "Have instructions l.ext* for sign extension"
+ default y
+ help
+ This config enables gcc to generate l.ext* instructions when compiling
+ the kernel which in general will improve performance and reduce the
+ binary size.
+
+ Select this if your implementation has support for the Class II
+ l.exths, l.extbs, l.exthz and l.extbz size extend instructions.
+
+ Say N if you are unsure.
+
endmenu
config NR_CPUS
diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile
index 760b734fb822..b446510173cd 100644
--- a/arch/openrisc/Makefile
+++ b/arch/openrisc/Makefile
@@ -21,6 +21,7 @@ OBJCOPYFLAGS := -O binary -R .note -R .comment -S
LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
KBUILD_CFLAGS += -pipe -ffixed-r10 -D__linux__
+KBUILD_CFLAGS += -msfimm -mshftimm
all: vmlinux.bin
@@ -38,6 +39,22 @@ else
KBUILD_CFLAGS += $(call cc-option,-msoft-div)
endif
+ifeq ($(CONFIG_OPENRISC_HAVE_INST_CMOV),y)
+ KBUILD_CFLAGS += $(call cc-option,-mcmov)
+endif
+
+ifeq ($(CONFIG_OPENRISC_HAVE_INST_ROR),y)
+ KBUILD_CFLAGS += $(call cc-option,-mror)
+endif
+
+ifeq ($(CONFIG_OPENRISC_HAVE_INST_RORI),y)
+ KBUILD_CFLAGS += $(call cc-option,-mrori)
+endif
+
+ifeq ($(CONFIG_OPENRISC_HAVE_INST_SEXT),y)
+ KBUILD_CFLAGS += $(call cc-option,-msext)
+endif
+
head-y := arch/openrisc/kernel/head.o
libs-y += $(LIBGCC)
--
2.31.1
next prev parent reply other threads:[~2022-05-15 12:42 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-15 12:41 [PATCH 00/13] OpenIRSC misc cleanups for 5.19 Stafford Horne
2022-05-15 12:41 ` Stafford Horne [this message]
2022-05-15 12:41 ` [PATCH 02/13] openrisc: Cleanup emergency print handling Stafford Horne
2022-05-15 16:03 ` Samuel Holland
2022-05-15 21:36 ` Stafford Horne
2022-05-15 12:41 ` [PATCH 03/13] openrisc: Add support for liteuart emergency printing Stafford Horne
2022-05-15 12:41 ` [PATCH 04/13] openrisc: Add syscall details to emergency syscall debugging Stafford Horne
2022-05-15 12:41 ` [PATCH 05/13] openrisc: Pretty print show_registers memory dumps Stafford Horne
2022-05-15 12:41 ` [PATCH 06/13] openrisc: Update litex defconfig to support glibc userland Stafford Horne
2022-05-15 12:41 ` [PATCH 07/13] openrisc/traps: Declare file scope symbols as static Stafford Horne
2022-05-15 12:41 ` [PATCH 08/13] openrisc/traps: Remove die_if_kernel function Stafford Horne
2022-05-15 12:41 ` [PATCH 09/13] openrisc/traps: Declare unhandled_exception for asmlinkage Stafford Horne
2022-05-15 12:41 ` [PATCH 10/13] openrisc/time: Fix symbol scope warnings Stafford Horne
2022-05-15 12:41 ` [PATCH 11/13] openrisc/delay: Add include to fix symbol not declared warning Stafford Horne
2022-05-15 12:41 ` [PATCH 12/13] openrisc/fault: Fix symbol scope warnings Stafford Horne
2022-05-15 12:41 ` [PATCH 13/13] openrisc: Remove unused IMMU tlb workardound Stafford Horne
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