From: Lai Jiangshan <jiangshanlai@gmail.com>
To: linux-kernel@vger.kernel.org
Cc: Borislav Petkov <bp@alien8.de>,
Peter Zijlstra <peterz@infradead.org>,
Josh Poimboeuf <jpoimboe@redhat.com>,
Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, Lai Jiangshan <jiangshan.ljs@antgroup.com>,
Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Kees Cook <keescook@chromium.org>,
Brian Gerst <brgerst@gmail.com>
Subject: [PATCH V2 3/7] x86: Mark __native_read_cr3() & native_write_cr3() as __always_inline
Date: Mon, 16 May 2022 21:17:34 +0800 [thread overview]
Message-ID: <20220516131739.521817-4-jiangshanlai@gmail.com> (raw)
In-Reply-To: <20220516131739.521817-1-jiangshanlai@gmail.com>
From: Lai Jiangshan <jiangshan.ljs@antgroup.com>
Mark __native_read_cr3() & native_write_cr3() as __always_inline to
ensure they are not instrumentable and in the .entry.text section if
the caller is not instrumentable and in the .entry.text section.
It prepares for __native_read_cr3() and native_write_cr3() to be used
in the C entry code for handling KPTI.
Signed-off-by: Lai Jiangshan <jiangshan.ljs@antgroup.com>
---
arch/x86/include/asm/special_insns.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
index 45b18eb94fa1..dbaee50abb3c 100644
--- a/arch/x86/include/asm/special_insns.h
+++ b/arch/x86/include/asm/special_insns.h
@@ -42,14 +42,14 @@ static __always_inline void native_write_cr2(unsigned long val)
asm volatile("mov %0,%%cr2": : "r" (val) : "memory");
}
-static inline unsigned long __native_read_cr3(void)
+static __always_inline unsigned long __native_read_cr3(void)
{
unsigned long val;
asm volatile("mov %%cr3,%0\n\t" : "=r" (val) : __FORCE_ORDER);
return val;
}
-static inline void native_write_cr3(unsigned long val)
+static __always_inline void native_write_cr3(unsigned long val)
{
asm volatile("mov %0,%%cr3": : "r" (val) : "memory");
}
--
2.19.1.6.gb485710b
next prev parent reply other threads:[~2022-05-16 13:17 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-16 13:17 [PATCH V2 0/7] x86/entry: Convert error_entry() to C code Lai Jiangshan
2022-05-16 13:17 ` [PATCH V2 1/7] x86/entry: Introduce __entry_text for entry code written in C Lai Jiangshan
2022-05-16 13:17 ` [PATCH V2 2/7] x86/entry: Move PTI_USER_* to arch/x86/include/asm/processor-flags.h Lai Jiangshan
2022-05-16 13:17 ` Lai Jiangshan [this message]
2022-05-16 13:17 ` [PATCH V2 4/7] x86/entry: Add arch/x86/entry/entry64.c for C entry code Lai Jiangshan
2022-05-16 13:17 ` [PATCH V2 5/7] x86/entry: Add the C verion of SWITCH_TO_KERNEL_CR3 as switch_to_kernel_cr3() Lai Jiangshan
2022-05-16 13:17 ` [PATCH V2 6/7] x86/traps: Add fence_swapgs_{user,kernel}_entry() and user_entry_swapgs_and_fence() Lai Jiangshan
2022-05-16 13:17 ` [PATCH V2 7/7] x86/entry: Implement the whole error_entry() as C code Lai Jiangshan
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