From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C2DAC433F5 for ; Mon, 23 May 2022 06:01:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234750AbiEWGBp (ORCPT ); Mon, 23 May 2022 02:01:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231721AbiEWGBI (ORCPT ); Mon, 23 May 2022 02:01:08 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 338A0389D; Sun, 22 May 2022 23:01:05 -0700 (PDT) X-UUID: 9bdd047790c641d884b9d4202a7736ca-20220523 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:02171810-ac98-49d5-a8e1-9efe00544e29,OB:10,L OB:10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham, ACTION:release,TS:90 X-CID-INFO: VERSION:1.1.5,REQID:02171810-ac98-49d5-a8e1-9efe00544e29,OB:10,LOB :10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D, ACTION:quarantine,TS:90 X-CID-META: VersionHash:2a19b09,CLOUDID:b77a2ee3-edbf-4bd4-8a34-dfc5f7bb086d,C OID:f98e2ab6fcf5,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:0,BEC:nil X-UUID: 9bdd047790c641d884b9d4202a7736ca-20220523 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 810586857; Mon, 23 May 2022 14:00:57 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 23 May 2022 14:00:57 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 23 May 2022 14:00:57 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v8 00/19] Cleanup MediaTek clk reset drivers and support SoCs Date: Mon, 23 May 2022 14:00:37 +0800 Message-ID: <20220523060056.24396-1-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In this series, we cleanup MediaTek clock reset drivers in clk/mediatek folder. MediaTek clock reset driver is used to provide reset control of modules controlled in clk, like infra_ao. Changes for v8: 1. Use 'enum mtk_reset_version' to replace u8 in patch 5 and 6. 2. Use lowercase '0xc' in patch 7. 3. Drop "simple-mfd" in patch 16 because it's for original reset controller. 4. v8 is based on linux-next next-20220520 and Chen-Yu's series[1]. Changes for v7: 1. v7 is based on linux-next next-20220519 and Chen-Yu's series[1]. 2. Add support for MT8186. [1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=643003 Changes for v6: 1. Add a new patch to support inuput argument index mode. 2. Revise definition in reset.h to index. Rex-BC Chen (19): clk: mediatek: reset: Add reset.h clk: mediatek: reset: Fix written reset bit offset clk: mediatek: reset: Refine and reorder functions in reset.c clk: mediatek: reset: Extract common drivers to update function clk: mediatek: reset: Merge and revise reset register function clk: mediatek: reset: Revise structure to control reset register clk: mediatek: reset: Support nonsequence base offsets of reset registers clk: mediatek: reset: Support inuput argument index mode clk: mediatek: reset: Change return type for clock reset register function clk: mediatek: reset: Add new register reset function with device clk: mediatek: reset: Add reset support for simple probe dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195 clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195 arm64: dts: mediatek: Add infra #reset-cells property for MT8192 arm64: dts: mediatek: Add infra #reset-cells property for MT8195 dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186 dt-bindings: arm: mediatek: Add #reset-cells property for MT8186 clk: mediatek: reset: Add infra_ao reset support for MT8186 .../mediatek/mediatek,mt8186-sys-clock.yaml | 3 + .../mediatek/mediatek,mt8192-sys-clock.yaml | 3 + .../mediatek/mediatek,mt8195-sys-clock.yaml | 3 + arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 + arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +- drivers/clk/mediatek/clk-mt2701-eth.c | 10 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 10 +- drivers/clk/mediatek/clk-mt2701-hif.c | 10 +- drivers/clk/mediatek/clk-mt2701.c | 22 +- drivers/clk/mediatek/clk-mt2712.c | 22 +- drivers/clk/mediatek/clk-mt7622-eth.c | 10 +- drivers/clk/mediatek/clk-mt7622-hif.c | 12 +- drivers/clk/mediatek/clk-mt7622.c | 22 +- drivers/clk/mediatek/clk-mt7629-eth.c | 10 +- drivers/clk/mediatek/clk-mt7629-hif.c | 12 +- drivers/clk/mediatek/clk-mt8135.c | 22 +- drivers/clk/mediatek/clk-mt8173.c | 22 +- drivers/clk/mediatek/clk-mt8183.c | 18 +- drivers/clk/mediatek/clk-mt8186-infra_ao.c | 23 ++ drivers/clk/mediatek/clk-mt8192.c | 29 +++ drivers/clk/mediatek/clk-mt8195-infra_ao.c | 24 +++ drivers/clk/mediatek/clk-mtk.c | 7 + drivers/clk/mediatek/clk-mtk.h | 9 +- drivers/clk/mediatek/reset.c | 198 +++++++++++++----- drivers/clk/mediatek/reset.h | 82 ++++++++ include/dt-bindings/reset/mt8186-resets.h | 5 + include/dt-bindings/reset/mt8192-resets.h | 8 + include/dt-bindings/reset/mt8195-resets.h | 6 + 28 files changed, 523 insertions(+), 95 deletions(-) create mode 100644 drivers/clk/mediatek/reset.h -- 2.18.0