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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id t18-20020a4adbd2000000b0040eb1d3f43dsm2330707oou.2.2022.06.02.06.43.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 06:43:55 -0700 (PDT) Received: (nullmailer pid 2175981 invoked by uid 1000); Thu, 02 Jun 2022 13:43:54 -0000 Date: Thu, 2 Jun 2022 08:43:54 -0500 From: Rob Herring To: Nobuhiro Iwamatsu Cc: Joerg Roedel , Will Deacon , yuji2.ishikawa@toshiba.co.jp, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/3] iommu: bindings: Add binding documentation for Toshiba Visconti5 IOMMU device Message-ID: <20220602134354.GA2170842-robh@kernel.org> References: <20220525013147.2215355-1-nobuhiro1.iwamatsu@toshiba.co.jp> <20220525013147.2215355-3-nobuhiro1.iwamatsu@toshiba.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220525013147.2215355-3-nobuhiro1.iwamatsu@toshiba.co.jp> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 25, 2022 at 10:31:46AM +0900, Nobuhiro Iwamatsu wrote: > Add documentation for the binding of Toshiba Visconti5 SoC's IOMMU. > > Signed-off-by: Nobuhiro Iwamatsu > --- > .../bindings/iommu/toshiba,visconti-atu.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iommu/toshiba,visconti-atu.yaml > > diff --git a/Documentation/devicetree/bindings/iommu/toshiba,visconti-atu.yaml b/Documentation/devicetree/bindings/iommu/toshiba,visconti-atu.yaml > new file mode 100644 > index 000000000000..af8d6688fa70 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iommu/toshiba,visconti-atu.yaml > @@ -0,0 +1,62 @@ > +# SPDX-License-Identifier: GPL-2.0-only Dual license: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iommu/toshiba,visconti-atu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Toshiba ARM SoC Visconti5 IOMMU (ATU) > + > +maintainers: > + - Nobuhiro Iwamatsu > + > +description: |+ > + IOMMU (ATU) driver can bse used for Visconti5's multimedia IPs, such as Bindings are for hardware, not drivers. > + DCNN (Deep Convolutional Neural Network), VIIF(Video Input), VOIF(Video > + output), and others. > + > +properties: > + compatible: > + const: toshiba,visconti-atu > + > + reg: > + maxItems: 1 > + > + "#iommu-cells": > + const: 0 > + > + toshiba,max-entry: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: The size of entry for address > + enum: > + - 16 > + - 32 > + > + toshiba,reserved-entry: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: The reserve number of entry address. > + default: 0 > + minimum: 0 > + maximum: 32 These 2 need a better description of what they are for. > + > +required: > + - compatible > + - reg > + - "#iommu-cells" > + - toshiba,max-entry > + > +additionalProperties: false > + > +examples: > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + atu_affine0: iommu@1400f000 { Drop unused labels. > + compatible = "toshiba,visconti-atu"; > + reg = <0 0x1400F000 0 0x1000>; > + toshiba,max-entry = <16>; > + toshiba,reserved-entry = <1>; > + #iommu-cells = <0>; > + }; > + }; > -- > 2.36.0 > > >