From: Bjorn Helgaas <helgaas@kernel.org>
To: Palmer Dabbelt <palmer@rivosinc.com>
Cc: Conor.Dooley@microchip.com, Greg KH <gregkh@linuxfoundation.org>,
Arnd Bergmann <arnd@arndb.de>,
mturquette@baylibre.com, sboyd@kernel.org,
linux-clk@vger.kernel.org, lorenzo.pieralisi@arm.com,
robh@kernel.org, kw@linux.com, linux-pci@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, Daire.McNamara@microchip.com,
Lewis.Hanly@microchip.com, Cyril.Jean@microchip.com
Subject: Re: [PATCH v4 1/1] MAINTAINERS: add polarfire rng, pci and clock drivers
Date: Thu, 2 Jun 2022 11:03:25 -0500 [thread overview]
Message-ID: <20220602160325.GA20054@bhelgaas> (raw)
In-Reply-To: <mhng-5c57560e-a00b-4fd8-95ee-5e2fc0dcd34c@palmer-ri-x1c9>
On Wed, Jun 01, 2022 at 06:55:40PM -0700, Palmer Dabbelt wrote:
> On Mon, 23 May 2022 13:00:01 PDT (-0700), Conor.Dooley@microchip.com wrote:
> > On 23/05/2022 20:52, Palmer Dabbelt wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> On Mon, 23 May 2022 04:42:53 PDT (-0700), Conor.Dooley@microchip.com wrote:
> >>> On 05/05/2022 11:55, Conor Dooley wrote:
> >>>> Hardware random, PCI and clock drivers for the PolarFire SoC have been
> >>>> upstreamed but are not covered by the MAINTAINERS entry, so add them.
> >>>> Daire is the author of the clock & PCI drivers, so add him as a
> >>>> maintainer in place of Lewis.
> >>>>
> >>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >>>
> >>> Hey Palmer,
> >>> I know youre busy etc but just a reminder :)
> >>
> >> Sorry, I didn't realize this was aimed at the RISC-V tree. I'm fine
> >> taking it, but it seems like these should have gone in along with the
> >> drivers.
> >
> > Yeah, sorry. In hindsight it should've but that ship has sailed. I sent
> > the rng bundled this way b/c I didn't want to end up a conflict.
> > Obv. there's not a rush so I can always split it back out if needs be.
>
> I'm adding a bunch of subsystem maintainers just to check again. I
> don't have any problem with it, just not really a RISC-V thing and don't
> wan to make a mess. I've stashed it over at palmer/pcsoc-maintainers
> for now.
Fine with me, if you want it:
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> >> Arnd: maybe this is really an SOC tree sort of thing? No big deal
> >> either way on my end, just let me know.
> >>
> >>> Thanks,
> >>> Conor.
> >>>
> >>>> ---
> >>>> MAINTAINERS | 5 ++++-
> >>>> 1 file changed, 4 insertions(+), 1 deletion(-)
> >>>>
> >>>> diff --git a/MAINTAINERS b/MAINTAINERS
> >>>> index fd768d43e048..d7602658b0a5 100644
> >>>> --- a/MAINTAINERS
> >>>> +++ b/MAINTAINERS
> >>>> @@ -16939,12 +16939,15 @@ N: riscv
> >>>> K: riscv
> >>>>
> >>>> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
> >>>> -M: Lewis Hanly <lewis.hanly@microchip.com>
> >>>> M: Conor Dooley <conor.dooley@microchip.com>
> >>>> +M: Daire McNamara <daire.mcnamara@microchip.com>
> >>>> L: linux-riscv@lists.infradead.org
> >>>> S: Supported
> >>>> F: arch/riscv/boot/dts/microchip/
> >>>> +F: drivers/char/hw_random/mpfs-rng.c
> >>>> +F: drivers/clk/microchip/clk-mpfs.c
> >>>> F: drivers/mailbox/mailbox-mpfs.c
> >>>> +F: drivers/pci/controller/pcie-microchip-host.c
> >>>> F: drivers/soc/microchip/
> >>>> F: include/soc/microchip/mpfs.h
> >>>>
> >>>
> >
next prev parent reply other threads:[~2022-06-02 16:03 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-05 10:55 [PATCH v4 0/1] polarfire soc kconfig/maintainers updates Conor Dooley
2022-05-05 10:55 ` [PATCH v4 1/1] MAINTAINERS: add polarfire rng, pci and clock drivers Conor Dooley
2022-05-23 11:42 ` Conor.Dooley
2022-05-23 19:52 ` Palmer Dabbelt
2022-05-23 20:00 ` Conor.Dooley
2022-06-02 1:55 ` Palmer Dabbelt
2022-06-02 4:39 ` Conor.Dooley
2022-06-02 16:31 ` Bjorn Helgaas
2022-06-02 22:05 ` Palmer Dabbelt
2022-06-02 16:03 ` Bjorn Helgaas [this message]
2022-06-09 22:43 ` Stephen Boyd
2022-06-09 22:53 ` Conor.Dooley
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