From: Ravi Bangoria <ravi.bangoria@amd.com>
To: <acme@kernel.org>
Cc: <ravi.bangoria@amd.com>, <kan.liang@linux.intel.com>,
<namhyung@kernel.org>, <jolsa@kernel.org>, <irogers@google.com>,
<peterz@infradead.org>, <rrichter@amd.com>, <mingo@redhat.com>,
<mark.rutland@arm.com>, <tglx@linutronix.de>, <bp@alien8.de>,
<james.clark@arm.com>, <leo.yan@linaro.org>, <ak@linux.intel.com>,
<eranian@google.com>, <like.xu.linux@gmail.com>, <x86@kernel.org>,
<linux-perf-users@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <sandipan.das@amd.com>,
<ananth.narayan@amd.com>, <kim.phillips@amd.com>,
<santosh.shukla@amd.com>
Subject: [PATCH v6 6/8] perf/x86/ibs: Add new IBS register bits into header
Date: Sat, 4 Jun 2022 10:15:17 +0530 [thread overview]
Message-ID: <20220604044519.594-7-ravi.bangoria@amd.com> (raw)
In-Reply-To: <20220604044519.594-1-ravi.bangoria@amd.com>
IBS support has been enhanced with two new features in upcoming uarch:
1. DataSrc extension and 2. L3 miss filtering. Additional set of bits
has been introduced in IBS registers to exploit these features. Define
these new bits into arch/x86/ header.
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Acked-by: Ian Rogers <irogers@google.com>
---
arch/x86/include/asm/amd-ibs.h | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
index aabdbb5ab920..f3eb098d63d4 100644
--- a/arch/x86/include/asm/amd-ibs.h
+++ b/arch/x86/include/asm/amd-ibs.h
@@ -29,7 +29,10 @@ union ibs_fetch_ctl {
rand_en:1, /* 57: random tagging enable */
fetch_l2_miss:1,/* 58: L2 miss for sampled fetch
* (needs IbsFetchComp) */
- reserved:5; /* 59-63: reserved */
+ l3_miss_only:1, /* 59: Collect L3 miss samples only */
+ fetch_oc_miss:1,/* 60: Op cache miss for the sampled fetch */
+ fetch_l3_miss:1,/* 61: L3 cache miss for the sampled fetch */
+ reserved:2; /* 62-63: reserved */
};
};
@@ -38,14 +41,14 @@ union ibs_op_ctl {
__u64 val;
struct {
__u64 opmaxcnt:16, /* 0-15: periodic op max. count */
- reserved0:1, /* 16: reserved */
+ l3_miss_only:1, /* 16: Collect L3 miss samples only */
op_en:1, /* 17: op sampling enable */
op_val:1, /* 18: op sample valid */
cnt_ctl:1, /* 19: periodic op counter control */
opmaxcnt_ext:7, /* 20-26: upper 7 bits of periodic op maximum count */
- reserved1:5, /* 27-31: reserved */
+ reserved0:5, /* 27-31: reserved */
opcurcnt:27, /* 32-58: periodic op counter current count */
- reserved2:5; /* 59-63: reserved */
+ reserved1:5; /* 59-63: reserved */
};
};
@@ -71,11 +74,12 @@ union ibs_op_data {
union ibs_op_data2 {
__u64 val;
struct {
- __u64 data_src:3, /* 0-2: data source */
+ __u64 data_src_lo:3, /* 0-2: data source low */
reserved0:1, /* 3: reserved */
rmt_node:1, /* 4: destination node */
cache_hit_st:1, /* 5: cache hit state */
- reserved1:57; /* 5-63: reserved */
+ data_src_hi:2, /* 6-7: data source high */
+ reserved1:56; /* 8-63: reserved */
};
};
--
2.31.1
next prev parent reply other threads:[~2022-06-04 4:47 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-04 4:45 [PATCH v6 0/8] perf/amd: Zen4 IBS extensions support (tool changes) Ravi Bangoria
2022-06-04 4:45 ` [PATCH v6 1/8] perf record ibs: Warn about sampling period skew Ravi Bangoria
2022-06-04 4:45 ` [PATCH v6 2/8] perf tool: Parse pmu caps sysfs only once Ravi Bangoria
2022-06-04 4:45 ` [PATCH v6 3/8] perf headers: Pass "cpu" pmu name while printing caps Ravi Bangoria
2022-06-04 4:45 ` [PATCH v6 4/8] perf headers: Store pmu caps in an array of strings Ravi Bangoria
2022-06-04 4:45 ` [PATCH v6 5/8] perf headers: Record non-cpu pmu capabilities Ravi Bangoria
2022-06-04 4:45 ` Ravi Bangoria [this message]
2022-07-27 12:09 ` [tip: perf/core] perf/x86/ibs: Add new IBS register bits into header tip-bot2 for Ravi Bangoria
2022-06-04 4:45 ` [PATCH v6 7/8] perf tool ibs: Sync amd ibs header file Ravi Bangoria
2022-06-04 4:45 ` [PATCH v6 8/8] perf script ibs: Support new IBS bits in raw trace dump Ravi Bangoria
2022-06-06 23:46 ` [PATCH v6 0/8] perf/amd: Zen4 IBS extensions support (tool changes) Namhyung Kim
2022-06-24 16:19 ` Arnaldo Carvalho de Melo
2022-06-27 4:20 ` Ravi Bangoria
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220604044519.594-7-ravi.bangoria@amd.com \
--to=ravi.bangoria@amd.com \
--cc=acme@kernel.org \
--cc=ak@linux.intel.com \
--cc=ananth.narayan@amd.com \
--cc=bp@alien8.de \
--cc=eranian@google.com \
--cc=irogers@google.com \
--cc=james.clark@arm.com \
--cc=jolsa@kernel.org \
--cc=kan.liang@linux.intel.com \
--cc=kim.phillips@amd.com \
--cc=leo.yan@linaro.org \
--cc=like.xu.linux@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
--cc=rrichter@amd.com \
--cc=sandipan.das@amd.com \
--cc=santosh.shukla@amd.com \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).