From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
To: "Edgecombe, Rick P" <rick.p.edgecombe@intel.com>
Cc: "peterz@infradead.org" <peterz@infradead.org>,
"Lutomirski, Andy" <luto@kernel.org>,
"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"hjl.tools@gmail.com" <hjl.tools@gmail.com>,
"linux-mm@kvack.org" <linux-mm@kvack.org>,
"kcc@google.com" <kcc@google.com>,
"andreyknvl@gmail.com" <andreyknvl@gmail.com>,
"ak@linux.intel.com" <ak@linux.intel.com>,
"dvyukov@google.com" <dvyukov@google.com>,
"x86@kernel.org" <x86@kernel.org>,
"ryabinin.a.a@gmail.com" <ryabinin.a.a@gmail.com>,
"glider@google.com" <glider@google.com>
Subject: Re: [PATCHv3 4/8] x86/mm: Handle LAM on context switch
Date: Wed, 15 Jun 2022 18:54:36 +0300 [thread overview]
Message-ID: <20220615155436.5fvosccsqbpscli4@black.fi.intel.com> (raw)
In-Reply-To: <d1a5615633f5e0376d7a75c1d8d12bbd89a7a63e.camel@intel.com>
On Fri, Jun 10, 2022 at 11:55:02PM +0000, Edgecombe, Rick P wrote:
> On Fri, 2022-06-10 at 17:35 +0300, Kirill A. Shutemov wrote:
> > @@ -687,6 +716,7 @@ void initialize_tlbstate_and_flush(void)
> > struct mm_struct *mm = this_cpu_read(cpu_tlbstate.loaded_mm);
> > u64 tlb_gen = atomic64_read(&init_mm.context.tlb_gen);
> > unsigned long cr3 = __read_cr3();
> > + u64 lam = cr3 & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57);
> >
> > /* Assert that CR3 already references the right mm. */
> > WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd));
> > @@ -700,7 +730,7 @@ void initialize_tlbstate_and_flush(void)
> > !(cr4_read_shadow() & X86_CR4_PCIDE));
> >
> > /* Force ASID 0 and force a TLB flush. */
> > - write_cr3(build_cr3(mm->pgd, 0));
> > + write_cr3(build_cr3(mm->pgd, 0, lam));
> >
>
> Can you explain why to keep the lam bits that were in CR3 here? It
> seems to be worried some CR3 bits got changed and need to be set to a
> known state. Why not take them from the MM?
>
> Also, it warns if the cr3 pfn doesn't match the mm pgd, should it warn
> if cr3 lam bits don't match the MM's copy?
You are right, taking LAM mode from init_mm is more correct. And we need
to update tlbstate with the new LAM mode.
I think both CR3 and init_mm should LAM disabled here as we are bringing
CPU up. I'll add WARN_ON().
--
Kirill A. Shutemov
next prev parent reply other threads:[~2022-06-15 15:54 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-10 14:35 [PATCHv3 0/8] Linear Address Masking enabling Kirill A. Shutemov
2022-06-10 14:35 ` [PATCHv3 1/8] x86/mm: Fix CR3_ADDR_MASK Kirill A. Shutemov
2022-06-10 23:32 ` Edgecombe, Rick P
2022-06-10 14:35 ` [PATCHv3 2/8] x86: CPUID and CR3/CR4 flags for Linear Address Masking Kirill A. Shutemov
2022-06-10 14:35 ` [PATCHv3 3/8] mm: Pass down mm_struct to untagged_addr() Kirill A. Shutemov
2022-06-10 23:33 ` Edgecombe, Rick P
2022-06-17 15:27 ` Alexander Potapenko
2022-06-17 22:38 ` Kirill A. Shutemov
2022-06-10 14:35 ` [PATCHv3 4/8] x86/mm: Handle LAM on context switch Kirill A. Shutemov
2022-06-10 23:55 ` Edgecombe, Rick P
2022-06-15 15:54 ` Kirill A. Shutemov [this message]
2022-06-16 9:08 ` Peter Zijlstra
2022-06-16 16:40 ` Kirill A. Shutemov
2022-06-17 15:35 ` Alexander Potapenko
2022-06-17 22:39 ` Kirill A. Shutemov
2022-06-28 23:33 ` Andy Lutomirski
2022-06-29 0:34 ` Kirill A. Shutemov
2022-06-30 1:51 ` Andy Lutomirski
2022-06-10 14:35 ` [PATCHv3 5/8] x86/uaccess: Provide untagged_addr() and remove tags before address check Kirill A. Shutemov
2022-06-13 17:36 ` Edgecombe, Rick P
2022-06-15 16:58 ` Kirill A. Shutemov
2022-06-15 19:06 ` Edgecombe, Rick P
2022-06-16 9:30 ` Peter Zijlstra
2022-06-16 16:44 ` Kirill A. Shutemov
2022-06-17 11:36 ` Peter Zijlstra
2022-06-17 14:22 ` H.J. Lu
2022-06-17 14:28 ` Peter Zijlstra
2022-06-16 9:34 ` Peter Zijlstra
2022-06-16 10:02 ` Peter Zijlstra
2022-06-16 16:48 ` Kirill A. Shutemov
2022-06-28 23:40 ` Andy Lutomirski
2022-06-29 0:42 ` Kirill A. Shutemov
2022-06-30 2:38 ` Andy Lutomirski
2022-07-05 0:13 ` Kirill A. Shutemov
2022-06-10 14:35 ` [PATCHv3 6/8] x86/mm: Provide ARCH_GET_UNTAG_MASK and ARCH_ENABLE_TAGGED_ADDR Kirill A. Shutemov
2022-06-10 15:25 ` Edgecombe, Rick P
2022-06-10 18:04 ` Kirill A. Shutemov
2022-06-10 16:16 ` Edgecombe, Rick P
2022-06-10 18:06 ` Kirill A. Shutemov
2022-06-10 18:08 ` Edgecombe, Rick P
2022-06-10 22:18 ` Edgecombe, Rick P
2022-06-11 1:12 ` Kirill A. Shutemov
2022-06-11 2:36 ` Edgecombe, Rick P
2022-06-12 21:03 ` Andy Lutomirski
2022-06-16 9:44 ` Peter Zijlstra
2022-06-16 16:54 ` Kirill A. Shutemov
2022-06-30 2:04 ` Andy Lutomirski
2022-06-13 14:42 ` Michal Hocko
2022-06-16 17:05 ` Kirill A. Shutemov
2022-06-19 23:40 ` Kirill A. Shutemov
2022-06-16 9:39 ` Peter Zijlstra
2022-06-28 23:42 ` Andy Lutomirski
2022-06-29 0:53 ` Kirill A. Shutemov
2022-06-30 2:29 ` Andy Lutomirski
2022-07-01 15:38 ` Kirill A. Shutemov
2022-07-02 23:55 ` Andy Lutomirski
2022-07-04 13:43 ` Kirill A. Shutemov
2022-06-10 14:35 ` [PATCHv3 7/8] x86: Expose untagging mask in /proc/$PID/arch_status Kirill A. Shutemov
2022-06-10 15:24 ` Dave Hansen
2022-06-11 1:28 ` Kirill A. Shutemov
2022-06-27 12:00 ` Catalin Marinas
2022-06-10 14:35 ` [PATCHv3 OPTIONAL 8/8] x86/mm: Extend LAM to support to LAM_U48 Kirill A. Shutemov
2022-06-16 10:00 ` Peter Zijlstra
2022-06-10 20:22 ` [PATCHv3 0/8] Linear Address Masking enabling Kostya Serebryany
2022-06-16 22:52 ` Edgecombe, Rick P
2022-06-16 23:43 ` Kirill A. Shutemov
2022-06-16 23:48 ` Edgecombe, Rick P
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