From: Nikita Shubin <nikita.shubin@maquefel.me>
To: Atish Patra <atishp@atishpatra.org>
Cc: "Anup Patel" <anup@brainfault.org>,
"João Mário Domingos" <joao.mario@tecnico.ulisboa.pt>,
linux <linux@yadro.com>, "Nikita Shubin" <n.shubin@yadro.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
"Arnaldo Carvalho de Melo" <acme@kernel.org>,
"Ingo Molnar" <mingo@redhat.com>, "Jiri Olsa" <jolsa@kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
linux-perf-users@vger.kernel.org,
linux-riscv <linux-riscv@lists.infradead.org>,
"Mark Rutland" <mark.rutland@arm.com>,
"Namhyung Kim" <namhyung@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Will Deacon" <will@kernel.org>
Subject: Re: [PATCH v4 0/5] RISC-V: Create unique identification for SoC PMU
Date: Sat, 25 Jun 2022 08:39:16 +0300 [thread overview]
Message-ID: <20220625083916.66e75def@redslave.neermore.group> (raw)
In-Reply-To: <CAOnJCU+2mOMj7MPzLKVZQ46gRs=ghxP6FK6oWkss0DfN_si3DQ@mail.gmail.com>
Hello Atish!
On Fri, 24 Jun 2022 10:05:34 -0700
Atish Patra <atishp@atishpatra.org> wrote:
> On Fri, Jun 24, 2022 at 9:01 AM Nikita Shubin
> <nikita.shubin@maquefel.me> wrote:
> >
> > From: Nikita Shubin <n.shubin@yadro.com>
> >
> > This series aims to provide matching vendor SoC with corresponded
> > JSON bindings.
> >
> > The ID string is proposed to be in form of
> > MVENDORID-MARCHID-MIMPID, for example for Sifive Unmatched the
> > corresponding string will be:
> >
> > 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
> >
> > Where MIMPID can vary as all impl supported the same number of
> > events, this might not be true for all future SoC however.
> >
> > Also added 3 counters which are standart for all RISC-V
> > implementations and SBI firmware events prerry names, as any
> > firmware that supports SBI PMU should also support firmare events.
> >
> > Link:
> > https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
> > Link:
> > https://patchwork.kernel.org/project/linux-riscv/list/?series=648017
> > --- v3->v4:
> > - drop pmuid in riscv_pmu_sbi, we are using /proc/cpuinfo
> > - rework util/header.c to use /proc/cpuinfo
> > - add SBI firmware events
> > - add firmware and std arch events to U74 pmu bindings
> > - change U74 id string and description in mapfile.csv
> > ---
> > Nikita Shubin (5):
> > drivers/perf: riscv_pmu_sbi: perf format
> > perf tools riscv: Add support for get_cpuid_str function
> > perf arch events: riscv arch std event files
> > perf arch events: riscv sbi firmare std event files
> > perf vendor events riscv: add Sifive U74 JSON file
> >
> > drivers/perf/riscv_pmu_sbi.c | 20 +++
> > tools/perf/arch/riscv/util/Build | 1 +
> > tools/perf/arch/riscv/util/header.c | 109 ++++++++++++++
> > tools/perf/pmu-events/arch/riscv/mapfile.csv | 17 +++
> > .../pmu-events/arch/riscv/riscv-generic.json | 20 +++
> > .../arch/riscv/riscv-sbi-firmware.json | 134
> > ++++++++++++++++++ .../arch/riscv/sifive/u74/firmware.json |
> > 68 +++++++++ .../arch/riscv/sifive/u74/generic.json | 11 ++
> > .../arch/riscv/sifive/u74/instructions.json | 92 ++++++++++++
> > .../arch/riscv/sifive/u74/memory.json | 32 +++++
> > .../arch/riscv/sifive/u74/microarch.json | 57 ++++++++
> > 11 files changed, 561 insertions(+)
> > create mode 100644 tools/perf/arch/riscv/util/header.c
> > create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
> > create mode 100644
> > tools/perf/pmu-events/arch/riscv/riscv-generic.json create mode
> > 100644 tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> > create mode 100644
> > tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json create
> > mode 100644
> > tools/perf/pmu-events/arch/riscv/sifive/u74/generic.json create
> > mode 100644
> > tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
> > create mode 100644
> > tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json create mode
> > 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
> >
> > --
> > 2.35.1
> >
>
> Thanks Nikita for reworking on the patches. It is good to specify that
> this series now depends
> on Anup's patch[1] that adds the mvendorid/mimpid to the
> /proc/cpuinfo.
>
> [1] https://lkml.org/lkml/2022/6/20/498
>
I will correct the remarks and fire a v5 next week then, hope some more
comments will rise for current version.
Do you have any thoughts or comments on cpuid form
"MVENDORID-MARCHID-MIMPID" ?
prev parent reply other threads:[~2022-06-25 5:39 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-24 16:00 [PATCH v4 0/5] RISC-V: Create unique identification for SoC PMU Nikita Shubin
2022-06-24 16:00 ` [PATCH v4 1/5] drivers/perf: riscv_pmu_sbi: perf format Nikita Shubin
2022-06-24 16:51 ` Atish Patra
2022-06-27 10:56 ` Will Deacon
2022-06-24 16:00 ` [PATCH v4 2/5] perf tools riscv: Add support for get_cpuid_str function Nikita Shubin
2022-06-24 16:32 ` Arnaldo Carvalho de Melo
2022-06-25 5:28 ` Nikita Shubin
2022-06-24 16:00 ` [PATCH v4 3/5] perf arch events: riscv arch std event files Nikita Shubin
2022-06-24 17:01 ` Atish Patra
2022-06-25 5:32 ` Nikita Shubin
2022-06-24 16:00 ` [PATCH v4 4/5] perf arch events: riscv sbi firmware " Nikita Shubin
2022-06-24 16:00 ` [PATCH v4 5/5] perf vendor events riscv: add Sifive U74 JSON file Nikita Shubin
2022-06-24 17:05 ` [PATCH v4 0/5] RISC-V: Create unique identification for SoC PMU Atish Patra
2022-06-25 5:39 ` Nikita Shubin [this message]
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