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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	p.zabel@pengutronix.de
Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
	vkoul@kernel.org, kishon@ti.com, rtanwar@maxlinear.com,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH v1 2/9] dt-bindings: reset: intel,rcu-gw: Allow up to three global reset items
Date: Tue, 28 Jun 2022 14:44:34 +0200	[thread overview]
Message-ID: <20220628124441.2385023-3-martin.blumenstingl@googlemail.com> (raw)
In-Reply-To: <20220628124441.2385023-1-martin.blumenstingl@googlemail.com>

Legacy SoCs use three elements for the global reset:
- offset
- reset bit
- status bit

Allow this in the dt-bindings as well.

Fixes: b7ab0cb00d086b ("dt-bindings: reset: Add YAML schemas for the Intel Reset controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
index 13bf6bb3f097..be64f8597710 100644
--- a/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
+++ b/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
@@ -22,11 +22,15 @@ properties:
   intel,global-reset:
     description: Global reset register offset and bit offset.
     $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 2
     items:
       - description: Register offset
       - description: Register bit offset
         minimum: 0
         maximum: 31
+      - description: Status bit offset (only if "#reset-cells" is 3)
+        minimum: 0
+        maximum: 31
 
   "#reset-cells":
     minimum: 2
-- 
2.36.1


  parent reply	other threads:[~2022-06-28 12:45 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-28 12:44 [PATCH v1 0/9] reset: replace reset-lantiq with reset-intel-gw Martin Blumenstingl
2022-06-28 12:44 ` [PATCH v1 1/9] dt-bindings: phy: lantiq: xway-rcu-usb2-phy: Convert to YAML Martin Blumenstingl
2022-07-01 16:25   ` Rob Herring
2022-06-28 12:44 ` Martin Blumenstingl [this message]
2022-07-01 16:26   ` [PATCH v1 2/9] dt-bindings: reset: intel,rcu-gw: Allow up to three global reset items Rob Herring
2022-06-28 12:44 ` [PATCH v1 3/9] dt-bindings: reset: intel,rcu-gw: Update bindings for "legacy" SoCs Martin Blumenstingl
2022-07-01 16:33   ` Rob Herring
2022-07-02 23:04     ` Martin Blumenstingl
2022-07-12 15:21       ` Rob Herring
2022-06-28 12:44 ` [PATCH v1 4/9] dt-bindings: mips: lantiq: rcu: Remove binding documentation Martin Blumenstingl
2022-07-01 16:34   ` Rob Herring
2022-06-28 12:44 ` [PATCH v1 5/9] reset: intel: Allow enabling the driver on "LANTIQ" (MIPS) platforms Martin Blumenstingl
2022-06-28 12:44 ` [PATCH v1 6/9] reset: intel: Add and update compatible strings Lantiq SoCs Martin Blumenstingl
2022-06-28 12:44 ` [PATCH v1 7/9] reset: intel: Use syscon_node_to_regmap on legacy SoCs Martin Blumenstingl
2022-06-28 12:44 ` [PATCH v1 8/9] reset: lantiq: Remove driver as it has been replaced by reset-intel-gw Martin Blumenstingl
2022-06-28 12:44 ` [PATCH v1 9/9] mips: dts: lantiq: Update the RCU node to match the intel,rcu-gw binding Martin Blumenstingl

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