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From: Mike Leach <mike.leach@linaro.org>
To: suzuki.poulose@arm.com, coresight@lists.linaro.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: mathieu.poirier@linaro.org, peterz@infradead.org,
	mingo@redhat.com, acme@kernel.org,
	linux-perf-users@vger.kernel.org, leo.yan@linaro.org,
	quic_jinlmao@quicinc.com, Mike Leach <mike.leach@linaro.org>
Subject: [PATCH v2 08/13] perf: cs-etm: Move mapping of Trace ID and cpu into helper function
Date: Mon,  4 Jul 2022 09:11:44 +0100	[thread overview]
Message-ID: <20220704081149.16797-9-mike.leach@linaro.org> (raw)
In-Reply-To: <20220704081149.16797-1-mike.leach@linaro.org>

The information to associate Trace ID and CPU will be changing.
Drivers will start outputting this as a hardware ID packet in the data
file and setting the value in AUXINFO to an unused value.

To prepare for this, we only map Trace ID and CPU data from AUXINFO if the
header version and values are valid, and move the mapping into a
helper function.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
---
 tools/perf/util/cs-etm.c | 53 +++++++++++++++++++++++++++-------------
 tools/perf/util/cs-etm.h | 14 +++++++++--
 2 files changed, 48 insertions(+), 19 deletions(-)

diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index 8b95fb3c4d7b..df9d67901f8d 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -193,6 +193,30 @@ int cs_etm__get_pid_fmt(u8 trace_chan_id, u64 *pid_fmt)
 	return 0;
 }
 
+static int cs_etm__map_trace_id(u8 trace_chan_id, u64 *cpu_metadata)
+{
+	struct int_node *inode;
+
+	/* Get an RB node for this CPU */
+	inode = intlist__findnew(traceid_list, trace_chan_id);
+
+	/* Something went wrong, no need to continue */
+	if (!inode)
+		return -ENOMEM;
+
+	/*
+	 * The node for that CPU should not be taken.
+	 * Back out if that's the case.
+	 */
+	if (inode->priv)
+		return -EINVAL;
+
+	/* All good, associate the traceID with the metadata pointer */
+	inode->priv = cpu_metadata;
+
+	return 0;
+}
+
 void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq,
 					      u8 trace_chan_id)
 {
@@ -2886,7 +2910,6 @@ int cs_etm__process_auxtrace_info(union perf_event *event,
 {
 	struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info;
 	struct cs_etm_auxtrace *etm = NULL;
-	struct int_node *inode;
 	unsigned int pmu_type;
 	int event_header_size = sizeof(struct perf_event_header);
 	int info_header_size;
@@ -2898,6 +2921,7 @@ int cs_etm__process_auxtrace_info(union perf_event *event,
 	u64 *ptr, *hdr = NULL;
 	u64 **metadata = NULL;
 	u64 hdr_version;
+	u8 trace_chan_id;
 
 	/*
 	 * sizeof(auxtrace_info_event::type) +
@@ -2991,25 +3015,20 @@ int cs_etm__process_auxtrace_info(union perf_event *event,
 			goto err_free_metadata;
 		}
 
-		/* Get an RB node for this CPU */
-		inode = intlist__findnew(traceid_list, metadata[j][trcidr_idx]);
-
-		/* Something went wrong, no need to continue */
-		if (!inode) {
-			err = -ENOMEM;
-			goto err_free_metadata;
-		}
-
 		/*
-		 * The node for that CPU should not be taken.
-		 * Back out if that's the case.
+		 * Associate a trace ID with metadata.
+		 * Later versions of the drivers will make this association using a
+		 * hardware ID packet in the data file, setting the value in AUXINFO to an
+		 * invalid trace ID value. Only map here if the value is valid.
 		 */
-		if (inode->priv) {
-			err = -EINVAL;
-			goto err_free_metadata;
+		if (hdr_version <  CS_AUX_HW_ID_VERSION_MIN) {
+			trace_chan_id = metadata[j][trcidr_idx];
+			if (CS_IS_VALID_TRACE_ID(trace_chan_id)) {
+				err = cs_etm__map_trace_id(trace_chan_id, metadata[j]);
+				if (err)
+					goto err_free_metadata;
+			}
 		}
-		/* All good, associate the traceID with the metadata pointer */
-		inode->priv = metadata[j];
 	}
 
 	/*
diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h
index 90c83f932d9a..712a6f855f0e 100644
--- a/tools/perf/util/cs-etm.h
+++ b/tools/perf/util/cs-etm.h
@@ -28,13 +28,17 @@ enum {
 /*
  * Update the version for new format.
  *
- * New version 1 format adds a param count to the per cpu metadata.
+ * Version 1: format adds a param count to the per cpu metadata.
  * This allows easy adding of new metadata parameters.
  * Requires that new params always added after current ones.
  * Also allows client reader to handle file versions that are different by
  * checking the number of params in the file vs the number expected.
+ *
+ * Version 2: Drivers will use PERF_RECORD_AUX_OUTPUT_HW_ID to output
+ * CoreSight Trace ID. ...TRACEIDR metadata will be set to unused ID.
  */
-#define CS_HEADER_CURRENT_VERSION 1
+#define CS_HEADER_CURRENT_VERSION	2
+#define CS_AUX_HW_ID_VERSION_MIN	2
 
 /* Beginning of header common to both ETMv3 and V4 */
 enum {
@@ -85,6 +89,12 @@ enum {
 	CS_ETE_PRIV_MAX
 };
 
+/*
+ * Check for valid CoreSight trace ID. If an invalid value is present in the metadata,
+ * then IDs are present in the hardware ID packet in the data file.
+ */
+#define CS_IS_VALID_TRACE_ID(id) ((id > 0) && (id < 0x70))
+
 /*
  * ETMv3 exception encoding number:
  * See Embedded Trace Macrocell specification (ARM IHI 0014Q)
-- 
2.17.1


  parent reply	other threads:[~2022-07-04  8:12 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-04  8:11 [PATCH v2 00/13] coresight: Add new API to allocate trace source ID values Mike Leach
2022-07-04  8:11 ` [PATCH v2 01/13] coresight: trace-id: Add API to dynamically assign Trace " Mike Leach
2022-07-19 17:30   ` Suzuki K Poulose
2022-08-09 16:11     ` Mike Leach
2022-07-04  8:11 ` [PATCH v2 02/13] coresight: trace-id: update CoreSight core to use Trace ID API Mike Leach
2022-07-19 17:36   ` Suzuki K Poulose
2022-07-04  8:11 ` [PATCH v2 03/13] coresight: stm: Update STM driver " Mike Leach
2022-07-19 17:51   ` Suzuki K Poulose
2022-07-04  8:11 ` [PATCH v2 04/13] coresight: etm4x: Update ETM4 " Mike Leach
2022-07-19 21:41   ` Suzuki K Poulose
2022-07-04  8:11 ` [PATCH v2 05/13] coresight: etm3x: Update ETM3 " Mike Leach
2022-07-19 21:45   ` Suzuki K Poulose
2022-07-04  8:11 ` [PATCH v2 06/13] coresight: etmX.X: stm: Remove unused legacy source Trace ID ops Mike Leach
2022-07-19 21:47   ` Suzuki K Poulose
2022-07-04  8:11 ` [PATCH v2 07/13] coresight: perf: traceid: Add perf notifiers for Trace ID Mike Leach
2022-07-19 21:49   ` Suzuki K Poulose
2022-07-04  8:11 ` Mike Leach [this message]
2022-07-19 14:54   ` [PATCH v2 08/13] perf: cs-etm: Move mapping of Trace ID and cpu into helper function James Clark
2022-07-20 10:22     ` Mike Leach
2022-07-20 12:57       ` James Clark
2022-07-20 16:19       ` Arnaldo Carvalho de Melo
2022-07-04  8:11 ` [PATCH v2 09/13] perf: cs-etm: Update record event to use new Trace ID protocol Mike Leach
2022-07-20 14:41   ` James Clark
2022-08-09 16:13     ` Mike Leach
2022-08-09 16:19       ` Arnaldo Carvalho de Melo
2022-08-23  9:11       ` James Clark
2022-07-04  8:11 ` [PATCH v2 10/13] kernel: events: Export perf_report_aux_output_id() Mike Leach
2022-07-19 21:50   ` Suzuki K Poulose
2022-07-04  8:11 ` [PATCH v2 11/13] perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet Mike Leach
2022-07-20 16:07   ` James Clark
2022-07-21 12:38     ` Mike Leach
2022-07-22  9:30       ` James Clark
2022-07-04  8:11 ` [PATCH v2 12/13] coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID Mike Leach
2022-07-20  9:30   ` Suzuki K Poulose
2022-07-20 10:53     ` Mike Leach
2022-07-04  8:11 ` [PATCH v2 13/13] coresight: trace-id: Add debug & test macros to Trace ID allocation Mike Leach
2022-07-20  9:41   ` Suzuki K Poulose
2022-07-21 10:27 ` [PATCH v2 00/13] coresight: Add new API to allocate trace source ID values James Clark
2022-07-21 13:54   ` Mike Leach
2022-07-22 12:10     ` James Clark
2022-07-25  8:19       ` Mike Leach
2022-07-26 13:53         ` James Clark
2022-07-26 14:57           ` Mike Leach

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