From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE886C433EF for ; Wed, 6 Jul 2022 11:44:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233150AbiGFLot (ORCPT ); Wed, 6 Jul 2022 07:44:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232950AbiGFLoc (ORCPT ); Wed, 6 Jul 2022 07:44:32 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C471286FB for ; Wed, 6 Jul 2022 04:44:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657107865; x=1688643865; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Y9U1WhJAWoCyuEBJ9cdgbIqAVPEHAMhulLIhS8kamw=; b=iA6U0xV0dwfeFjrcwGKYdFPO9He9icZeN2uG61c5K2iyjOPM6IE7eEBN 0IU066fGjt7h359RIxaBov79Coscxt6Djfb0jjQiNR6euhvQTcFUUpah/ QxGmS401KpQ1KkWzaYvfPkybEV9F409eiL6yLf1Fbww11rBIuWVqtK8rh rZuN1AniIu8wW3+bZwzeQHLddu//lpOj3JvH3n629UdGBQ0a/D8+VKqlb kqkjk3w46//1cNjDZmPnnsDJZoLnYEwp7V8038lPN9LNPugloBlNuhpiG EFeIIPDmeYVV1EVo5nwtgrJhoSPWObFKlfGGfZ/IrzaX58DqS1cQpedlr w==; X-IronPort-AV: E=McAfee;i="6400,9594,10399"; a="347707466" X-IronPort-AV: E=Sophos;i="5.92,249,1650956400"; d="scan'208";a="347707466" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2022 04:44:12 -0700 X-IronPort-AV: E=Sophos;i="5.92,249,1650956400"; d="scan'208";a="650630147" Received: from sannilnx.jer.intel.com ([10.12.26.175]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2022 04:44:09 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 04/14] drm/i915/gsc: add GSC XeHP SDV platform definition Date: Wed, 6 Jul 2022 14:43:35 +0300 Message-Id: <20220706114345.1128018-5-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220706114345.1128018-1-alexander.usyskin@intel.com> References: <20220706114345.1128018-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Define GSC on XeHP SDV (Intel(R) dGPU without display) XeHP SDV uses the same hardware settings as DG1, but uses polling instead of interrupts and runs the firmware in slow pace due to hardware limitations. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c index f963c220bbff..bfc307e49bf9 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = { } }; +static const struct gsc_def gsc_def_xehpsdv[] = { + { + /* HECI1 not enabled on the device. */ + }, + { + .name = "mei-gscfi", + .bar = DG1_GSC_HECI2_BASE, + .bar_size = GSC_BAR_LENGTH, + .use_polling = true, + .slow_fw = true, + } +}; + static const struct gsc_def gsc_def_dg2[] = { { .name = "mei-gsc", @@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915, if (IS_DG1(i915)) { def = &gsc_def_dg1[intf_id]; + } else if (IS_XEHPSDV(i915)) { + def = &gsc_def_xehpsdv[intf_id]; } else if (IS_DG2(i915)) { def = &gsc_def_dg2[intf_id]; } else { -- 2.34.1