From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: bp@alien8.de
Cc: linux-tip-commits@vger.kernel.org, peterz@infradead.org,
dave.hansen@linux.intel.com, rafael.j.wysocki@intel.com,
rui.zhang@intel.com, x86@kernel.org,
linux-kernel@vger.kernel.org, chang.seok.bae@intel.com
Subject: [PATCH][Rebased] intel_idle: Add a new flag to initialize the AMX state
Date: Mon, 18 Jul 2022 11:56:11 -0700 [thread overview]
Message-ID: <20220718185611.20030-1-chang.seok.bae@intel.com> (raw)
In-Reply-To: <YtUimvkv+rDJJ9zu@zn.tnic>
The non-initialized AMX state can be the cause of C-state demotion from C6
to C1E. This low-power idle state may improve power savings and thus result
in a higher available turbo frequency budget.
This behavior is implementation-specific. Initialize the state for the C6
entrance of Sapphire Rapids as needed.
Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Tested-by: Zhang Rui <rui.zhang@intel.com>
Link: https://lkml.kernel.org/r/20220608164748.11864-3-chang.seok.bae@intel.com
Link: https://lkml.kernel.org/r/20220614164116.5196-1-chang.seok.bae@intel.com
[ changb: Rebased to the upstream again. ]
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
---
The patch merged in the tip's x86/fpu has conflict with the retbleed patch
-- commit bf5835bcdb96 ("intel_idle: Disable IBRS during long idle") as of
v5.19-rc7.
---
drivers/idle/intel_idle.c | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index f5c6802aa6c3..1ec221079367 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -56,6 +56,7 @@
#include <asm/nospec-branch.h>
#include <asm/mwait.h>
#include <asm/msr.h>
+#include <asm/fpu/api.h>
#define INTEL_IDLE_VERSION "0.5.1"
@@ -113,6 +114,11 @@ static unsigned int mwait_substates __initdata;
*/
#define CPUIDLE_FLAG_IBRS BIT(16)
+/*
+ * Initialize large xstate for the C6-state entrance.
+ */
+#define CPUIDLE_FLAG_INIT_XSTATE BIT(17)
+
/*
* MWAIT takes an 8-bit "hint" in EAX "suggesting"
* the C-state (top nibble) and sub-state (bottom nibble)
@@ -185,6 +191,13 @@ static __cpuidle int intel_idle_ibrs(struct cpuidle_device *dev,
return ret;
}
+static __cpuidle int intel_idle_xstate(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
+{
+ fpu_idle_fpregs();
+ return __intel_idle(dev, drv, index);
+}
+
/**
* intel_idle_s2idle - Ask the processor to enter the given idle state.
* @dev: cpuidle device of the target CPU.
@@ -200,8 +213,12 @@ static __cpuidle int intel_idle_ibrs(struct cpuidle_device *dev,
static __cpuidle int intel_idle_s2idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
- unsigned long eax = flg2MWAIT(drv->states[index].flags);
unsigned long ecx = 1; /* break on interrupt flag */
+ struct cpuidle_state *state = &drv->states[index];
+ unsigned long eax = flg2MWAIT(state->flags);
+
+ if (state->flags & CPUIDLE_FLAG_INIT_XSTATE)
+ fpu_idle_fpregs();
mwait_idle_with_hints(eax, ecx);
@@ -936,7 +953,8 @@ static struct cpuidle_state spr_cstates[] __initdata = {
{
.name = "C6",
.desc = "MWAIT 0x20",
- .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED |
+ CPUIDLE_FLAG_INIT_XSTATE,
.exit_latency = 290,
.target_residency = 800,
.enter = &intel_idle,
@@ -1851,6 +1869,9 @@ static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
drv->states[drv->state_count].enter = intel_idle_ibrs;
}
+ if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_INIT_XSTATE)
+ drv->states[drv->state_count].enter = intel_idle_xstate;
+
if ((disabled_states_mask & BIT(drv->state_count)) ||
((icpu->use_acpi || force_use_acpi) &&
intel_idle_off_by_default(mwait_hint) &&
--
2.17.1
prev parent reply other threads:[~2022-07-18 19:05 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-08 16:47 [PATCH v5 0/2] x86/fpu: Make AMX state ready for CPU idle Chang S. Bae
2022-06-08 16:47 ` [PATCH v5 1/2] x86/fpu: Add a helper to prepare AMX state for low-power " Chang S. Bae
2022-06-08 19:32 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2022-06-14 22:46 ` tip-bot2 for Chang S. Bae
2022-06-14 22:53 ` tip-bot2 for Chang S. Bae
2022-07-19 17:31 ` tip-bot2 for Chang S. Bae
2022-06-08 16:47 ` [PATCH v5 2/2] intel_idle: Add a new flag to initialize the AMX state Chang S. Bae
2022-06-08 19:32 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2022-06-09 10:23 ` Peter Zijlstra
2022-06-14 16:41 ` [PATCH][Rebased] " Chang S. Bae
2022-07-19 17:31 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
[not found] ` <38cd51750ef7b995506d001eae3e4ec872cf5b77.camel@linux.intel.com>
2022-06-14 17:23 ` [PATCH v5 2/2] " Chang S. Bae
2022-06-15 6:25 ` Artem Bityutskiy
2022-06-14 22:53 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2022-07-18 9:06 ` Borislav Petkov
2022-07-18 18:56 ` Chang S. Bae [this message]
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