From: Aradhya Bhatia <a-bhatia1@ti.com>
To: Tomi Valkeinen <tomba@kernel.org>, Jyri Sarha <jyri.sarha@iki.fi>,
Rob Herring <robh+dt@kernel.org>, David Airlie <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Darren Etheridge <detheridge@ti.com>, Nishanth Menon <nm@ti.com>,
Vignesh Raghavendra <vigneshr@ti.com>,
Rahul T R <r-ravikumar@ti.com>, Krunal Bhargav <k-bhargav@ti.com>,
Devarsh Thakkar <devarsht@ti.com>,
DRI Development List <dri-devel@lists.freedesktop.org>,
Devicetree List <devicetree@vger.kernel.org>,
Linux Kernel List <linux-kernel@vger.kernel.org>
Subject: [PATCH 8/8] drm/tidss: Enable Dual and Duplicate Modes for OLDI
Date: Tue, 19 Jul 2022 13:38:45 +0530 [thread overview]
Message-ID: <20220719080845.22122-9-a-bhatia1@ti.com> (raw)
In-Reply-To: <20220719080845.22122-1-a-bhatia1@ti.com>
The AM625 DSS peripheral supports 2 OLDI TXes which can work to enable 2
duplicated displays of smaller resolutions or enable a single Dual-Link
display with a higher resolution (1920x1200).
Configure the necessary register to enable the different modes.
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
---
drivers/gpu/drm/tidss/tidss_dispc.c | 44 +++++++++++++++++++++++++++--
1 file changed, 41 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index 0b9689453ee8..28cb61259471 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -1021,8 +1021,8 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport,
int count = 0;
/*
- * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC
- * bits of DISPC_VP_DSS_OLDI_CFG are set statically to 0.
+ * For the moment MASTERSLAVE, and SRC bits of DISPC_VP_DSS_OLDI_CFG are
+ * set statically to 0.
*/
if (fmt->data_width == 24)
@@ -1039,7 +1039,45 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport,
oldi_cfg |= BIT(0); /* ENABLE */
- dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
+ /*
+ * As per all the current implementations of DSS, the OLDI TXes are present only on
+ * hw_videoport = 0 (OLDI TX 0). However, the config register for 2nd OLDI TX (OLDI TX 1)
+ * is present in the address space of hw_videoport = 1. Hence, using "hw_videoport + 1" to
+ * configure OLDI TX 1.
+ */
+
+ switch (dispc->oldi_mode) {
+ case OLDI_MODE_OFF:
+ oldi_cfg &= ~BIT(0); /* DISABLE */
+ dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
+ dispc_vp_write(dispc, hw_videoport + 1, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
+ break;
+
+ case OLDI_SINGLE_LINK_SINGLE_MODE_0:
+ dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
+ break;
+
+ case OLDI_SINGLE_LINK_SINGLE_MODE_1:
+ dispc_vp_write(dispc, hw_videoport + 1, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
+ break;
+
+ case OLDI_SINGLE_LINK_DUPLICATE_MODE:
+ oldi_cfg |= BIT(5); /* DUPLICATE MODE */
+ dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
+ dispc_vp_write(dispc, hw_videoport + 1, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
+ break;
+
+ case OLDI_DUAL_LINK:
+ oldi_cfg |= BIT(11); /* DUALMODESYNC */
+ dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
+ dispc_vp_write(dispc, hw_videoport + 1, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
+ break;
+
+ default:
+ dev_warn(dispc->dev, "%s: Incorrect oldi mode. Returning.\n",
+ __func__);
+ return;
+ }
while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) &&
count < 10000)
--
2.37.0
next prev parent reply other threads:[~2022-07-19 8:09 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-19 8:08 sFrom b69208b75f7ae8e223c81783afb04fecd2f5faf8 Mon Sep 17 00:00:00 2001 Aradhya Bhatia
2022-07-19 8:08 ` [PATCH 1/8] dt-bindings: display: ti,am65x-dss: Add port properties for DSS Aradhya Bhatia
2022-07-20 23:28 ` Rob Herring
2022-07-22 16:16 ` Nishanth Menon
2022-07-28 6:28 ` Tomi Valkeinen
2022-07-25 11:26 ` Aradhya Bhatia
2022-07-25 22:14 ` Francesco Dolcini
2022-08-10 17:48 ` Rob Herring
2022-07-28 11:16 ` Tomi Valkeinen
2022-07-19 8:08 ` [PATCH 2/8] dt-bindings: display: ti,am65x-dss: Add IO CTRL property for AM625 OLDI Aradhya Bhatia
2022-07-20 23:32 ` Rob Herring
2022-07-25 11:34 ` Aradhya Bhatia
2022-07-19 8:08 ` [PATCH 3/8] drm/tidss: Add support for DSS port properties Aradhya Bhatia
2022-07-28 12:07 ` Tomi Valkeinen
2022-07-19 8:08 ` [PATCH 4/8] drm/tidss: Add support for Dual Link LVDS Bus Format Aradhya Bhatia
2022-07-28 11:03 ` Tomi Valkeinen
2022-07-28 11:45 ` Tomi Valkeinen
2022-08-09 5:58 ` Aradhya Bhatia
2022-08-09 6:28 ` Tomi Valkeinen
2022-08-09 9:06 ` Aradhya Bhatia
2022-08-09 9:51 ` Tomi Valkeinen
2022-08-09 13:34 ` Aradhya Bhatia
2022-08-01 3:32 ` Aradhya Bhatia
2022-07-19 8:08 ` [PATCH 5/8] drm/tidss: dt property to force 16bit VP output to a 24bit bridge Aradhya Bhatia
2022-07-19 8:08 ` [PATCH 6/8] drm/tidss: Add IO CTRL and Power support for OLDI TX in AM625 Aradhya Bhatia
2022-07-19 8:08 ` [PATCH 7/8] drm/tidss: Fix clock request value for OLDI videoports Aradhya Bhatia
2022-07-28 10:05 ` Tomi Valkeinen
2022-07-29 3:56 ` Aradhya Bhatia
2022-07-29 8:13 ` Tomi Valkeinen
2022-07-19 8:08 ` Aradhya Bhatia [this message]
2022-07-27 13:22 ` [PATCH 8/8] drm/tidss: Enable Dual and Duplicate Modes for OLDI Tomi Valkeinen
2022-07-28 6:46 ` Tomi Valkeinen
2022-07-28 8:49 ` Aradhya Bhatia
2022-07-28 11:29 ` Tomi Valkeinen
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