* [PATCH V14 0/7] CXL: Read CDAT
@ 2022-07-15 3:04 ira.weiny
2022-07-15 3:04 ` [PATCH V14 1/7] PCI: Add vendor ID for the PCI SIG ira.weiny
` (7 more replies)
0 siblings, 8 replies; 20+ messages in thread
From: ira.weiny @ 2022-07-15 3:04 UTC (permalink / raw)
To: Dan Williams, Bjorn Helgaas, Jonathan Cameron
Cc: Ira Weiny, Lukas Wunner, Alison Schofield, Vishal Verma,
Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl, linux-pci
From: Ira Weiny <ira.weiny@intel.com>
Details of changes are in the individual patches.
Major changes from V13:[10]
Dan minor updates
Willy's suggestion of documentation is good but I'm deferring it until
we get the location of the PCI mailboxes settled.
Drop retry CDAT patch
Drop DSMAS patch
Rebased on latest cxl-pending
CXL drivers need various data which are provided through generic DOE mailboxes
as defined in the PCIe 6.0 spec.[1]
One such data is the Coherent Device Attribute Table (CDAT). CDAT data provides
coherent information about the various devices in the system. It was developed
because systems no longer have a priori knowledge of all coherent devices
within a system. CDAT describes the coherent characteristics of the
components on the CXL bus separate from system configurations. The OS can
then, for example, use this information to form correct interleave sets.
To begin reading the CDAT the OS must have support to access the DOE mailboxes
provided by the CXL devices.
Because DOE is not specific to DOE but is provided within the PCI spec, the
series adds PCI DOE capability library functions. These functions allow for
the iteration of the DOE capabilities on a device as well as creating
pci_doe_mb structures which can control the operation of the DOE state machine.
For now the iteration of and storage of the DOE mailboxes is done on memdev
objects within the CXL stack. When this is needed in more generic code this
can be lifted later.
This work was tested using qemu.
[0] https://lore.kernel.org/linux-cxl/20211105235056.3711389-1-ira.weiny@intel.com/
[1] https://pcisig.com/specifications
[2] https://lore.kernel.org/qemu-devel/20210202005948.241655-1-ben.widawsky@intel.com/
[3] https://lore.kernel.org/linux-cxl/20220201071952.900068-1-ira.weiny@intel.com/
[4] https://lore.kernel.org/linux-cxl/20220330235920.2800929-1-ira.weiny@intel.com/
[5] https://lore.kernel.org/linux-cxl/20220414203237.2198665-1-ira.weiny@intel.com/
[6] https://lore.kernel.org/linux-cxl/20220531152632.1397976-1-ira.weiny@intel.com/
[7] https://lore.kernel.org/linux-cxl/20220605005049.2155874-1-ira.weiny@intel.com/
[8] https://lore.kernel.org/linux-cxl/20220610202259.3544623-1-ira.weiny@intel.com/
[9] https://lore.kernel.org/linux-cxl/20220628041527.742333-1-ira.weiny@intel.com/
[10] https://lore.kernel.org/linux-cxl/20220705154932.2141021-1-ira.weiny@intel.com/
Previous changes
================
Changes from V12:[9]
A couple of bug fixes in the new XArray stuff
Remove the IRQ support because I did not realize how that worked and it
was complicating things.
Remove busy retries and replace with an error as there is no good way
to ensure it will work.
Other code clean ups mentioned in the individual patches.
Changes from V11:[8]
The major change in this version is to remove the workqueue from the
internal implementation of the state machine. A single ordered
workqueue within each mailbox processes tasks submitted. This
workqueue takes care of all locking and guarantees that tasks are
completed in the order submitted. Any synchronization which is
required between tasks will need to be handled by the user of the
mailbox. However, the user can depend on work items being completed in
the order they are submitted. So a single thread submitter is
guaranteed to get all work items completed in order. This also aids in
the support of a single mailbox supporting multiple protocols. Each
protocol could have a separate thread submitting tasks for that
protocol. The mailbox object will ensure that each protocol task is
complete before another task starts. But multiple user threads can be
submitting tasks for different protocols all at the same time without
regard to other protocols being used.
XArrays are used throughout the series.
Other minor changes are noted in the individual patches.
Changes from V10:[7]
Address Ben Widawsky's comments
Protect against potentially malicious devices.
Fix ownership issue of cdat_mb
Changes from V9:[6]
Address feedback from
Lukas Wunner, Davidlohr Bueso, Jonathan Cameron,
Alison Schofield, and Ben Widawsky
Details in each individual patch.
Changes from V8:[5]
For this version I've punted a bit to get it out and drop the auxiliary
bus functionality. I like where Jonathan is going with the port driver
idea. I think eventually the irq/mailbox creation will need to be more
generic in a PCI port driver. I've modeled this version on such an
architecture but used the CXL port for the time being.
From Dan
Drop the auxiliary bus/device
From Jonathan
Cleanups
From Bjorn
Clean up commit messages
move pci-doe.c to doe.c
Clean up PCI spec references
Ensure all messages use pci_*()
Add offset to error messages to distinguish mailboxes
use hex for DOE offsets
Print 4 nibbles for Vendor ID and 2 for type.
s/irq/IRQ in comments
Fix long lines
Fix typos
Changes from V7:[4]
Avoid code bloat by making pci-doe.c conditional on CONFIG_PCI_DOE
which is auto selected by the CXL_PCI config option.
Minor code clean ups
Fix bug in pci_doe_supports_prot()
Rebase to cxl-pending
Changes from V6:[3]
The big change is the removal of the auxiliary bus code from the PCI
layer. The auxiliary bus usage is now in the CXL layer. The PCI layer
provides helpers for subsystems to utilize DOE mailboxes by creating a
pci_doe_mb object which controls a state machine for that mailbox
capability. The CXL layer wraps this object in an auxiliary device and
driver which can then be used to determine if the kernel is controlling
the capability or it is available to be used by user space. Reads from
user space via lspci are allowed. Writes are allowed but flagged via a
tainting the kernel.
Feedback from Bjorn, Jonathan, and Dan
Details in each patch
Changes from V5:[0]
Rework the patch set to split PCI vs CXL changes
Also make each change a bit more stand alone for easier review
Add cxl_cdat structure
Put CDAT related data structures in cdat.h
Clarify some device lifetimes with comments
Incorporate feedback from Jonathan, Bjorn and Dan
The bigest change is placing the DOE scanning code into the
pci_doe driver (part of the PCI codre).
Validate the CDAT when it is read rather than before DSMAS
parsing
Do not report DSMAS failure as an error, report a warning and
keep going.
Retry reading the table 1 time.
Update commit messages and this cover letter
Ira Weiny (5):
PCI: Replace magic constant for PCI Sig Vendor ID
cxl/pci: Create PCI DOE mailbox's for memory devices
driver-core: Introduce BIN_ATTR_ADMIN_{RO,RW}
cxl/port: Read CDAT table
cxl/port: Introduce cxl_cdat_valid()
Jonathan Cameron (2):
PCI: Add vendor ID for the PCI SIG
PCI/DOE: Add DOE mailbox support functions
.clang-format | 1 +
Documentation/ABI/testing/sysfs-bus-cxl | 10 +
drivers/cxl/Kconfig | 1 +
drivers/cxl/cdat.h | 63 +++
drivers/cxl/core/pci.c | 206 +++++++++
drivers/cxl/cxl.h | 5 +
drivers/cxl/cxlmem.h | 3 +
drivers/cxl/cxlpci.h | 1 +
drivers/cxl/pci.c | 44 ++
drivers/cxl/port.c | 54 +++
drivers/pci/Kconfig | 3 +
drivers/pci/Makefile | 1 +
drivers/pci/doe.c | 546 ++++++++++++++++++++++++
drivers/pci/probe.c | 2 +-
include/linux/pci-doe.h | 79 ++++
include/linux/pci_ids.h | 1 +
include/linux/sysfs.h | 16 +
include/uapi/linux/pci_regs.h | 29 +-
18 files changed, 1063 insertions(+), 2 deletions(-)
create mode 100644 drivers/cxl/cdat.h
create mode 100644 drivers/pci/doe.c
create mode 100644 include/linux/pci-doe.h
base-commit: b060edfd8cdd52bc8648392500bf152a8dd6d4c5
--
2.35.3
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH V14 1/7] PCI: Add vendor ID for the PCI SIG
2022-07-15 3:04 [PATCH V14 0/7] CXL: Read CDAT ira.weiny
@ 2022-07-15 3:04 ` ira.weiny
2022-07-15 3:04 ` [PATCH V14 2/7] PCI: Replace magic constant for PCI Sig Vendor ID ira.weiny
` (6 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: ira.weiny @ 2022-07-15 3:04 UTC (permalink / raw)
To: Dan Williams, Bjorn Helgaas, Jonathan Cameron
Cc: Davidlohr Bueso, Lukas Wunner, Alison Schofield, Vishal Verma,
Ira Weiny, Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl,
linux-pci
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This ID is used in DOE headers to identify protocols that are defined
within the PCI Express Base Specification, PCIe r6.0, sec 6.30.1.1 table
6-32.
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
include/linux/pci_ids.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 0178823ce8c2..8af3b86206b1 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -151,6 +151,7 @@
#define PCI_CLASS_OTHERS 0xff
/* Vendors and devices. Sort key: vendor first, device next. */
+#define PCI_VENDOR_ID_PCI_SIG 0x0001
#define PCI_VENDOR_ID_LOONGSON 0x0014
--
2.35.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH V14 2/7] PCI: Replace magic constant for PCI Sig Vendor ID
2022-07-15 3:04 [PATCH V14 0/7] CXL: Read CDAT ira.weiny
2022-07-15 3:04 ` [PATCH V14 1/7] PCI: Add vendor ID for the PCI SIG ira.weiny
@ 2022-07-15 3:04 ` ira.weiny
2022-07-15 3:04 ` [PATCH V14 3/7] PCI/DOE: Add DOE mailbox support functions ira.weiny
` (5 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: ira.weiny @ 2022-07-15 3:04 UTC (permalink / raw)
To: Dan Williams, Bjorn Helgaas, Jonathan Cameron
Cc: Ira Weiny, Davidlohr Bueso, Lukas Wunner, Alison Schofield,
Vishal Verma, Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl,
linux-pci
From: Ira Weiny <ira.weiny@intel.com>
Replace the magic value in pci_bus_crs_vendor_id() with
PCI_VENDOR_ID_PCI_SIG.
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
---
Changes from V6
Simplify commit message
---
drivers/pci/probe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 17a969942d37..6280e780a48c 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2312,7 +2312,7 @@ EXPORT_SYMBOL(pci_alloc_dev);
static bool pci_bus_crs_vendor_id(u32 l)
{
- return (l & 0xffff) == 0x0001;
+ return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
}
static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
--
2.35.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH V14 3/7] PCI/DOE: Add DOE mailbox support functions
2022-07-15 3:04 [PATCH V14 0/7] CXL: Read CDAT ira.weiny
2022-07-15 3:04 ` [PATCH V14 1/7] PCI: Add vendor ID for the PCI SIG ira.weiny
2022-07-15 3:04 ` [PATCH V14 2/7] PCI: Replace magic constant for PCI Sig Vendor ID ira.weiny
@ 2022-07-15 3:04 ` ira.weiny
2022-07-19 16:35 ` Jonathan Cameron
2022-07-15 3:04 ` [PATCH V14 4/7] cxl/pci: Create PCI DOE mailbox's for memory devices ira.weiny
` (4 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: ira.weiny @ 2022-07-15 3:04 UTC (permalink / raw)
To: Dan Williams, Bjorn Helgaas, Jonathan Cameron
Cc: Li, Ming, Bjorn Helgaas, Matthew Wilcox, Ira Weiny, Lukas Wunner,
Alison Schofield, Vishal Verma, Dave Jiang, Ben Widawsky,
linux-kernel, linux-cxl, linux-pci
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Introduced in a PCIe r6.0, sec 6.30, DOE provides a config space based
mailbox with standard protocol discovery. Each mailbox is accessed
through a DOE Extended Capability.
Each DOE mailbox must support the DOE discovery protocol in addition to
any number of additional protocols.
Define core PCIe functionality to manage a single PCIe DOE mailbox at a
defined config space offset. Functionality includes iterating,
creating, query of supported protocol, and task submission. Destruction
of the mailboxes is device managed.
Cc: "Li, Ming" <ming4.li@intel.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>
Cc: Matthew Wilcox <willy@infradead.org>
Acked-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Co-developed-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
---
Changes from V13.1
Clean up docs
Dan:
pass up pci_doe_wait() error
use dev_err_ratelimited
Remove extra '{'
pass up xa_insert() return code
Use pci_name() and dev_driver_string() to name WQ
Changes from V13
Bjorn:
Update commit message
Put fmt strings on same line as pci_err
s/successful/successfully
Clean up line wrap on comments
Matthew:
Fix up shifting in xa_mk_value()
Changes from V12
Remove busy retries
s/pci_doe_xa_entry/pci_doe_xa_prot_entry
Open code pci_doe_abort call
s/ABORT/CANCEL
Clarify canceling a task by using a cancel flag instead
of 'abort' flag
Clean up comments
Jonathan:
use xa_mk_value() for XArray value
spaces around '-' operator
s/possitive/positive
s/pci_doe_issue_abort/pci_doe_abort
Remove pci_doe_free_mb() and use devm_* exclusively in pci_doe_create_mb()
s/ret/rc to be consistent
Remove irq support.
Clean up timeout values and ensure waits values are correct
Remove unnecessary arm_wait function
Changes from V11
Bjorn: s/PCI/PCIe
use dev_fmt
move cap_offset in struct pci_doe_mb
use break and return from a central place
fix interrupt prints
s/PCI_DOE_CAP_IRQ/PCI_DOE_CAP_INT_MSG_NUM
s/irq_msg_num/int_msg_num
when the value is not an irq but rather the
interrupt message number for the DOE
s/irq/IRQ in comments
Clarify request and response payload size units
In addition clarify the rv units Check for
invalid response payload size (must be at least
1 DW)
Dan: s/EOPNOTSUPP/ENXIO/
Add pci_doe_for_each_off to .clang-format
use xarray for supported protocols
s/pci_doe_create_mb/pcim_doe_create_mb/
Remove pci_doe_destroy_mb
Dan: Convert the statemachine to process tasks as work items
Define pci_doe_write_ctrl()
Introduce pci_doe_irq_enabled()
issue a stand alone abort
Don't go through the state machine for the abort. Just
poll/irq until the response comes back.
Remove Wait Abort state
A wait abort can just be triggered from outside and stop
the state machine from whatever loop it may be in.
Let the state machine issue the abort itself and wait
for it to return or not.
Remove Wait abort on error
Issue the abort directly before returning. Abort
failure will flag the MB dead.
Remove workqueue processing from state machine
clean up function locations in the file
Move abort flag/document it
React to an abort while aborting and bail. This will
mark the mailbox dead.
Convert task to a work item
Create a workqueue in the mailbox. Remove cur_task and
locking. Set DEAD when taking mailbox down.
print error on marking mailbox dead
Introduce signal_task_abort
flatten out the state machine
Changes from V9
Lukas Wunner
Update comments
Move private doe structures and defines from pci-doe.h to doe.c
check Data Obj Ready prior to last ack
Davidlohr
make task_lock a spinlock
Lukas/Jonathan
Remove special case of error in irq handler
Fix potential race with the scheduling of a task when one is ending.
The current task can't be retired until the state
machine is idle. Otherwise a new task work item may run
and the state machine would be out of sync.
Changes from V8
Remove Bjorn's ack
Expose a function to find the irq number for a mailbox based on
offset. This is the code Jonathan proposed for finding the irq
number here:
https://lore.kernel.org/linux-cxl/20220503153449.4088-2-Jonathan.Cameron@huawei.com/
This removes funky bool parameter to create.
Move pci_set_master() within the pci_doe_enable_irq()
Per Bjorn
Clean up commit messages
move pci-doe.c to doe.c
Clean up PCI spec references
Ensure all messages use pci_*()
Add offset to error messages to distinguish mailboxes
use hex for DOE offsets
Print 4 nibbles for Vendor ID and 2 for type.
s/irq/IRQ in comments
Fix long lines
Fix typos
Changes from V7
Add a Kconfig for this functionality
Fix bug in pci_doe_supports_prot()
Rebased on cxl-pending
Changes from V6
Clean up signed off by lines
Make this functionality all PCI library functions
Clean up header files
s/pci_doe_irq/pci_doe_irq_handler
Use pci_{request,free}_irq
Remove irq_name (maintained by pci_request_irq)
Fix checks to use an irq
Consistently use u16 for cap_offset
Cleanup kdocs and comments
Create a helper retire_cur_task() to handle locking of the
current task pointer.
Remove devm_ calls from PCI layer.
The devm_ calls do not allow for the pci_doe_mb objects
to be tied to an auxiliary device. Leave it to the
caller to use devm_ if desired.
From Dan Williams
s/cb/end_task/; Pass pci_doe_task to end_task
Clarify exchange/task/request/response.
Merge pci_doe_task and pci_doe_exchange into
pci_doe_task which represents a single
request/response task for the state machine to
process.
Simplify submitting work to the mailbox
Replace pci_doe_exchange_sync() with
pci_doe_submit_task() Consumers of the mailbox
are now responsible for setting up callbacks
within a task object and submitting them to the
mailbox to be processed.
Remove WARN_ON when task != NULL and be sure to abort that task.
Convert abort/dead to atomic flags
s/state_lock/task_lock to better define what the lock is
protecting
Remove all the auxiliary bus code from the PCI layer
The PCI layer provides helpers to use the DOE
Mailboxes. Each subsystem can then use the
helpers as they see fit. The CXL layer in this
series uses aux devices to manage the new
pci_doe_mb objects.
From Bjorn
Clarify the fact that DOE mailboxes are capabilities of
the device.
Code clean ups
Cleanup Makefile
Update references to PCI SIG spec v6.0
Move this attribution here:
This code is based on Jonathan's V4 series here:
https://lore.kernel.org/linux-cxl/20210524133938.2815206-1-Jonathan.Cameron@huawei.com/
Changes from V5
From Bjorn
s/pci_WARN/pci_warn
Add timeout period to print
Trim to 80 chars
Use Tabs for DOE define spacing
Use %#x for clarity
From Jonathan
Addresses concerns about the order of unwinding stuff
s/doe/doe_dev in pci_doe_exhcnage_sync
Correct kernel Doc comment
Move pci_doe_task_complete() down in the file.
Rework pci_doe_irq()
process STATUS_ERROR first
Return IRQ_NONE if the irq is not processed
Use PCI_DOE_STATUS_INT_STATUS explicitly to
clear the irq
Clean up goto label s/err_free_irqs/err_free_irq
use devm_kzalloc for doe struct
clean up error paths in pci_doe_probe
s/pci_doe_drv/pci_doe
remove include mutex.h
remove device name and define, move it in the next patch which uses it
use devm_kasprintf() for irq_name
use devm_request_irq()
remove pci_doe_unregister()
[get/put]_device() were unneeded and with the use of
devm_* this function can be removed completely.
refactor pci_doe_register and s/pci_doe_register/pci_doe_reg_irq
make this function just a registration of the irq and
move pci_doe_abort() into pci_doe_probe()
use devm_* to allocate the protocol array
Changes from Jonathan's V4
Move the DOE MB code into the DOE auxiliary driver
Remove Task List in favor of a wait queue
Changes from Ben
remove CXL references
propagate rc from pci functions on error
---
.clang-format | 1 +
drivers/pci/Kconfig | 3 +
drivers/pci/Makefile | 1 +
drivers/pci/doe.c | 546 ++++++++++++++++++++++++++++++++++
include/linux/pci-doe.h | 79 +++++
include/uapi/linux/pci_regs.h | 29 +-
6 files changed, 658 insertions(+), 1 deletion(-)
create mode 100644 drivers/pci/doe.c
create mode 100644 include/linux/pci-doe.h
diff --git a/.clang-format b/.clang-format
index 9b87ea1fc16e..1247d54f9e49 100644
--- a/.clang-format
+++ b/.clang-format
@@ -516,6 +516,7 @@ ForEachMacros:
- 'of_property_for_each_string'
- 'of_property_for_each_u32'
- 'pci_bus_for_each_resource'
+ - 'pci_doe_for_each_off'
- 'pcl_for_each_chunk'
- 'pcl_for_each_segment'
- 'pcm_for_each_format'
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 133c73207782..b2f2e588a817 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -121,6 +121,9 @@ config XEN_PCIDEV_FRONTEND
config PCI_ATS
bool
+config PCI_DOE
+ bool
+
config PCI_ECAM
bool
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 0da6b1ebc694..2680e4c92f0a 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_PCI_ECAM) += ecam.o
obj-$(CONFIG_PCI_P2PDMA) += p2pdma.o
obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o
obj-$(CONFIG_VGA_ARB) += vgaarb.o
+obj-$(CONFIG_PCI_DOE) += doe.o
# Endpoint library must be initialized before its users
obj-$(CONFIG_PCI_ENDPOINT) += endpoint/
diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c
new file mode 100644
index 000000000000..12c3762be22f
--- /dev/null
+++ b/drivers/pci/doe.c
@@ -0,0 +1,546 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Data Object Exchange
+ * PCIe r6.0, sec 6.30 DOE
+ *
+ * Copyright (C) 2021 Huawei
+ * Jonathan Cameron <Jonathan.Cameron@huawei.com>
+ *
+ * Copyright (C) 2022 Intel Corporation
+ * Ira Weiny <ira.weiny@intel.com>
+ */
+
+#define dev_fmt(fmt) "DOE: " fmt
+
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+#include <linux/mutex.h>
+#include <linux/pci.h>
+#include <linux/pci-doe.h>
+#include <linux/workqueue.h>
+
+#define PCI_DOE_PROTOCOL_DISCOVERY 0
+
+#define PCI_DOE_BUSY_MAX_RETRIES 16
+
+/* Timeout of 1 second from 6.30.2 Operation, PCI Spec r6.0 */
+#define PCI_DOE_TIMEOUT HZ
+#define PCI_DOE_POLL_INTERVAL (PCI_DOE_TIMEOUT / 128)
+
+#define PCI_DOE_FLAG_CANCEL 0
+#define PCI_DOE_FLAG_DEAD 1
+
+/**
+ * struct pci_doe_mb - State for a single DOE mailbox
+ *
+ * This state is used to manage a single DOE mailbox capability. All fields
+ * should be considered opaque to the consumers and the structure passed into
+ * the helpers below after being created by devm_pci_doe_create()
+ *
+ * @pdev: PCI device this mailbox belongs to
+ * @cap_offset: Capability offset
+ * @prots: Array of protocols supported (encoded as long values)
+ * @wq: Wait queue for work item
+ * @work_queue: Queue of pci_doe_work items
+ * @flags: Bit array of PCI_DOE_FLAG_* flags
+ */
+struct pci_doe_mb {
+ struct pci_dev *pdev;
+ u16 cap_offset;
+ struct xarray prots;
+
+ wait_queue_head_t wq;
+ struct workqueue_struct *work_queue;
+ unsigned long flags;
+};
+
+static int pci_doe_wait(struct pci_doe_mb *doe_mb, unsigned long timeout)
+{
+ if (wait_event_timeout(doe_mb->wq,
+ test_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags),
+ timeout))
+ return -EIO;
+ return 0;
+}
+
+static void pci_doe_write_ctrl(struct pci_doe_mb *doe_mb, u32 val)
+{
+ struct pci_dev *pdev = doe_mb->pdev;
+ int offset = doe_mb->cap_offset;
+
+ pci_write_config_dword(pdev, offset + PCI_DOE_CTRL, val);
+}
+
+static int pci_doe_abort(struct pci_doe_mb *doe_mb)
+{
+ struct pci_dev *pdev = doe_mb->pdev;
+ int offset = doe_mb->cap_offset;
+ unsigned long timeout_jiffies;
+
+ pci_dbg(pdev, "[%x] Issuing Abort\n", offset);
+
+ timeout_jiffies = jiffies + PCI_DOE_TIMEOUT;
+ pci_doe_write_ctrl(doe_mb, PCI_DOE_CTRL_ABORT);
+
+ do {
+ int rc;
+ u32 val;
+
+ rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL);
+ if (rc)
+ return rc;
+ pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
+
+ /* Abort success! */
+ if (!FIELD_GET(PCI_DOE_STATUS_ERROR, val) &&
+ !FIELD_GET(PCI_DOE_STATUS_BUSY, val))
+ return 0;
+
+ } while (!time_after(jiffies, timeout_jiffies));
+
+ /* Abort has timed out and the MB is dead */
+ pci_err(pdev, "[%x] ABORT timed out\n", offset);
+ return -EIO;
+}
+
+static int pci_doe_send_req(struct pci_doe_mb *doe_mb,
+ struct pci_doe_task *task)
+{
+ struct pci_dev *pdev = doe_mb->pdev;
+ int offset = doe_mb->cap_offset;
+ u32 val;
+ int i;
+
+ /*
+ * Check the DOE busy bit is not set. If it is set, this could indicate
+ * someone other than Linux (e.g. firmware) is using the mailbox. Note
+ * it is expected that firmware and OS will negotiate access rights via
+ * an, as yet to be defined method.
+ */
+ pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
+ if (FIELD_GET(PCI_DOE_STATUS_BUSY, val))
+ return -EBUSY;
+
+ if (FIELD_GET(PCI_DOE_STATUS_ERROR, val))
+ return -EIO;
+
+ /* Write DOE Header */
+ val = FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_VID, task->prot.vid) |
+ FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, task->prot.type);
+ pci_write_config_dword(pdev, offset + PCI_DOE_WRITE, val);
+ /* Length is 2 DW of header + length of payload in DW */
+ pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
+ FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH,
+ 2 + task->request_pl_sz /
+ sizeof(u32)));
+ for (i = 0; i < task->request_pl_sz / sizeof(u32); i++)
+ pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
+ task->request_pl[i]);
+
+ pci_doe_write_ctrl(doe_mb, PCI_DOE_CTRL_GO);
+
+ /* Request is sent - now wait for poll or IRQ */
+ return 0;
+}
+
+static bool pci_doe_data_obj_ready(struct pci_doe_mb *doe_mb)
+{
+ struct pci_dev *pdev = doe_mb->pdev;
+ int offset = doe_mb->cap_offset;
+ u32 val;
+
+ pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
+ if (FIELD_GET(PCI_DOE_STATUS_DATA_OBJECT_READY, val))
+ return true;
+ return false;
+}
+
+static int pci_doe_recv_resp(struct pci_doe_mb *doe_mb, struct pci_doe_task *task)
+{
+ struct pci_dev *pdev = doe_mb->pdev;
+ int offset = doe_mb->cap_offset;
+ size_t length, payload_length;
+ u32 val;
+ int i;
+
+ /* Read the first dword to get the protocol */
+ pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val);
+ if ((FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_VID, val) != task->prot.vid) ||
+ (FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, val) != task->prot.type)) {
+ dev_err_ratelimited(&pdev->dev, "[%x] expected [VID, Protocol] = [%04x, %02x], got [%04x, %02x]\n",
+ doe_mb->cap_offset, task->prot.vid, task->prot.type,
+ FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_VID, val),
+ FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, val));
+ return -EIO;
+ }
+
+ pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
+ /* Read the second dword to get the length */
+ pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val);
+ pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
+
+ length = FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH, val);
+ if (length > SZ_1M || length < 2)
+ return -EIO;
+
+ /* First 2 dwords have already been read */
+ length -= 2;
+ payload_length = min(length, task->response_pl_sz / sizeof(u32));
+ /* Read the rest of the response payload */
+ for (i = 0; i < payload_length; i++) {
+ pci_read_config_dword(pdev, offset + PCI_DOE_READ,
+ &task->response_pl[i]);
+ /* Prior to the last ack, ensure Data Object Ready */
+ if (i == (payload_length - 1) && !pci_doe_data_obj_ready(doe_mb))
+ return -EIO;
+ pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
+ }
+
+ /* Flush excess length */
+ for (; i < length; i++) {
+ pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val);
+ pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
+ }
+
+ /* Final error check to pick up on any since Data Object Ready */
+ pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
+ if (FIELD_GET(PCI_DOE_STATUS_ERROR, val))
+ return -EIO;
+
+ return min(length, task->response_pl_sz / sizeof(u32)) * sizeof(u32);
+}
+
+static void signal_task_complete(struct pci_doe_task *task, int rv)
+{
+ task->rv = rv;
+ task->complete(task);
+}
+
+static void signal_task_abort(struct pci_doe_task *task, int rv)
+{
+ struct pci_doe_mb *doe_mb = task->doe_mb;
+ struct pci_dev *pdev = doe_mb->pdev;
+
+ if (pci_doe_abort(doe_mb)) {
+ /*
+ * If the device can't process an abort; set the mailbox dead
+ * - no more submissions
+ */
+ pci_err(pdev, "[%x] Abort failed marking mailbox dead\n",
+ doe_mb->cap_offset);
+ set_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags);
+ }
+ signal_task_complete(task, rv);
+}
+
+static void doe_statemachine_work(struct work_struct *work)
+{
+ struct pci_doe_task *task = container_of(work, struct pci_doe_task,
+ work);
+ struct pci_doe_mb *doe_mb = task->doe_mb;
+ struct pci_dev *pdev = doe_mb->pdev;
+ int offset = doe_mb->cap_offset;
+ unsigned long timeout_jiffies;
+ u32 val;
+ int rc;
+
+ if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags)) {
+ signal_task_complete(task, -EIO);
+ return;
+ }
+
+ /* Send request */
+ rc = pci_doe_send_req(doe_mb, task);
+
+ if (rc) {
+ /*
+ * The specification does not provide any guidance on how to
+ * resolve conflicting requests from other entities.
+ * Furthermore, it is likely that busy will not be detected
+ * most of the time. Flag any detection of status busy with an
+ * error.
+ */
+ if (rc == -EBUSY)
+ dev_err_ratelimited(&pdev->dev, "[%x] busy detected; another entity is sending conflicting requests\n",
+ offset);
+ signal_task_abort(task, rc);
+ return;
+ }
+
+ timeout_jiffies = jiffies + PCI_DOE_TIMEOUT;
+ rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL);
+ if (rc) {
+ signal_task_abort(task, rc);
+ return;
+ }
+
+ /* Poll for response */
+retry_resp:
+ pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
+ if (FIELD_GET(PCI_DOE_STATUS_ERROR, val)) {
+ signal_task_abort(task, -EIO);
+ return;
+ }
+
+ if (!FIELD_GET(PCI_DOE_STATUS_DATA_OBJECT_READY, val)) {
+ if (time_after(jiffies, timeout_jiffies)) {
+ signal_task_abort(task, -EIO);
+ return;
+ }
+ rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL);
+ if (rc) {
+ signal_task_abort(task, rc);
+ return;
+ }
+ goto retry_resp;
+ }
+
+ rc = pci_doe_recv_resp(doe_mb, task);
+ if (rc < 0) {
+ signal_task_abort(task, rc);
+ return;
+ }
+
+ signal_task_complete(task, rc);
+}
+
+static void pci_doe_task_complete(struct pci_doe_task *task)
+{
+ complete(task->private);
+}
+
+static int pci_doe_discovery(struct pci_doe_mb *doe_mb, u8 *index, u16 *vid,
+ u8 *protocol)
+{
+ u32 request_pl = FIELD_PREP(PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX,
+ *index);
+ u32 response_pl;
+ DECLARE_COMPLETION_ONSTACK(c);
+ struct pci_doe_task task = {
+ .prot.vid = PCI_VENDOR_ID_PCI_SIG,
+ .prot.type = PCI_DOE_PROTOCOL_DISCOVERY,
+ .request_pl = &request_pl,
+ .request_pl_sz = sizeof(request_pl),
+ .response_pl = &response_pl,
+ .response_pl_sz = sizeof(response_pl),
+ .complete = pci_doe_task_complete,
+ .private = &c,
+ };
+ int rc;
+
+ rc = pci_doe_submit_task(doe_mb, &task);
+ if (rc < 0)
+ return rc;
+
+ wait_for_completion(&c);
+
+ if (task.rv != sizeof(response_pl))
+ return -EIO;
+
+ *vid = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID, response_pl);
+ *protocol = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL,
+ response_pl);
+ *index = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX,
+ response_pl);
+
+ return 0;
+}
+
+static void *pci_doe_xa_prot_entry(u16 vid, u8 prot)
+{
+ return xa_mk_value((vid << 8) | prot);
+}
+
+static int pci_doe_cache_protocols(struct pci_doe_mb *doe_mb)
+{
+ u8 index = 0;
+ u8 xa_idx = 0;
+
+ do {
+ int rc;
+ u16 vid;
+ u8 prot;
+
+ rc = pci_doe_discovery(doe_mb, &index, &vid, &prot);
+ if (rc)
+ return rc;
+
+ pci_dbg(doe_mb->pdev,
+ "[%x] Found protocol %d vid: %x prot: %x\n",
+ doe_mb->cap_offset, xa_idx, vid, prot);
+
+ rc = xa_insert(&doe_mb->prots, xa_idx++,
+ pci_doe_xa_prot_entry(vid, prot), GFP_KERNEL);
+ if (rc)
+ return rc;
+ } while (index);
+
+ return 0;
+}
+
+static void pci_doe_xa_destroy(void *mb)
+{
+ struct pci_doe_mb *doe_mb = mb;
+
+ xa_destroy(&doe_mb->prots);
+}
+
+static void pci_doe_destroy_workqueue(void *mb)
+{
+ struct pci_doe_mb *doe_mb = mb;
+
+ destroy_workqueue(doe_mb->work_queue);
+}
+
+static void pci_doe_flush_mb(void *mb)
+{
+ struct pci_doe_mb *doe_mb = mb;
+
+ /* Stop all pending work items from starting */
+ set_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags);
+
+ /* Cancel an in progress work item, if necessary */
+ set_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags);
+ wake_up(&doe_mb->wq);
+
+ /* Flush all work items */
+ flush_workqueue(doe_mb->work_queue);
+}
+
+/**
+ * pcim_doe_create_mb() - Create a DOE mailbox object
+ *
+ * @pdev: PCI device to create the DOE mailbox for
+ * @cap_offset: Offset of the DOE mailbox
+ *
+ * Create a single mailbox object to manage the mailbox protocol at the
+ * cap_offset specified.
+ *
+ * RETURNS: created mailbox object on success
+ * ERR_PTR(-errno) on failure
+ */
+struct pci_doe_mb *pcim_doe_create_mb(struct pci_dev *pdev, u16 cap_offset)
+{
+ struct pci_doe_mb *doe_mb;
+ struct device *dev = &pdev->dev;
+ int rc;
+
+ doe_mb = devm_kzalloc(dev, sizeof(*doe_mb), GFP_KERNEL);
+ if (!doe_mb)
+ return ERR_PTR(-ENOMEM);
+
+ doe_mb->pdev = pdev;
+ doe_mb->cap_offset = cap_offset;
+ init_waitqueue_head(&doe_mb->wq);
+
+ xa_init(&doe_mb->prots);
+ rc = devm_add_action(dev, pci_doe_xa_destroy, doe_mb);
+ if (rc)
+ return ERR_PTR(rc);
+
+ doe_mb->work_queue = alloc_ordered_workqueue("%s %s DOE [%x]", 0,
+ dev_driver_string(&pdev->dev),
+ pci_name(pdev),
+ doe_mb->cap_offset);
+ if (!doe_mb->work_queue) {
+ pci_err(pdev, "[%x] failed to allocate work queue\n",
+ doe_mb->cap_offset);
+ return ERR_PTR(-ENOMEM);
+ }
+ rc = devm_add_action_or_reset(dev, pci_doe_destroy_workqueue, doe_mb);
+ if (rc)
+ return ERR_PTR(rc);
+
+ /* Reset the mailbox by issuing an abort */
+ rc = pci_doe_abort(doe_mb);
+ if (rc) {
+ pci_err(pdev, "[%x] failed to reset mailbox with abort command : %d\n",
+ doe_mb->cap_offset, rc);
+ return ERR_PTR(rc);
+ }
+
+ /*
+ * The state machine and the mailbox should be in sync now;
+ * Set up mailbox flush prior to using the mailbox to query protocols.
+ */
+ rc = devm_add_action_or_reset(dev, pci_doe_flush_mb, doe_mb);
+ if (rc)
+ return ERR_PTR(rc);
+
+ rc = pci_doe_cache_protocols(doe_mb);
+ if (rc) {
+ pci_err(pdev, "[%x] failed to cache protocols : %d\n",
+ doe_mb->cap_offset, rc);
+ return ERR_PTR(rc);
+ }
+
+ return doe_mb;
+}
+EXPORT_SYMBOL_GPL(pcim_doe_create_mb);
+
+/**
+ * pci_doe_supports_prot() - Return if the DOE instance supports the given
+ * protocol
+ * @doe_mb: DOE mailbox capability to query
+ * @vid: Protocol Vendor ID
+ * @type: Protocol type
+ *
+ * RETURNS: True if the DOE mailbox supports the protocol specified
+ */
+bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type)
+{
+ unsigned long index;
+ void *entry;
+
+ /* The discovery protocol must always be supported */
+ if (vid == PCI_VENDOR_ID_PCI_SIG && type == PCI_DOE_PROTOCOL_DISCOVERY)
+ return true;
+
+ xa_for_each(&doe_mb->prots, index, entry)
+ if (entry == pci_doe_xa_prot_entry(vid, type))
+ return true;
+
+ return false;
+}
+EXPORT_SYMBOL_GPL(pci_doe_supports_prot);
+
+/**
+ * pci_doe_submit_task() - Submit a task to be processed by the state machine
+ *
+ * @doe_mb: DOE mailbox capability to submit to
+ * @task: task to be queued
+ *
+ * Submit a DOE task (request/response) to the DOE mailbox to be processed.
+ * Returns upon queueing the task object. If the queue is full this function
+ * will sleep until there is room in the queue.
+ *
+ * task->complete will be called when the state machine is done processing this
+ * task.
+ *
+ * Excess data will be discarded.
+ *
+ * RETURNS: 0 when task has been successfully queued, -ERRNO on error
+ */
+int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task)
+{
+ if (!pci_doe_supports_prot(doe_mb, task->prot.vid, task->prot.type))
+ return -EINVAL;
+
+ /*
+ * DOE requests must be a whole number of DW and the response needs to
+ * be big enough for at least 1 DW
+ */
+ if (task->request_pl_sz % sizeof(u32) ||
+ task->response_pl_sz < sizeof(u32))
+ return -EINVAL;
+
+ if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags))
+ return -EIO;
+
+ task->doe_mb = doe_mb;
+ INIT_WORK(&task->work, doe_statemachine_work);
+ queue_work(doe_mb->work_queue, &task->work);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pci_doe_submit_task);
diff --git a/include/linux/pci-doe.h b/include/linux/pci-doe.h
new file mode 100644
index 000000000000..c77f6258c996
--- /dev/null
+++ b/include/linux/pci-doe.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Data Object Exchange
+ * PCIe r6.0, sec 6.30 DOE
+ *
+ * Copyright (C) 2021 Huawei
+ * Jonathan Cameron <Jonathan.Cameron@huawei.com>
+ *
+ * Copyright (C) 2022 Intel Corporation
+ * Ira Weiny <ira.weiny@intel.com>
+ */
+
+#ifndef LINUX_PCI_DOE_H
+#define LINUX_PCI_DOE_H
+
+#include <linux/completion.h>
+
+struct pci_doe_protocol {
+ u16 vid;
+ u8 type;
+};
+
+struct pci_doe_mb;
+
+/**
+ * struct pci_doe_task - represents a single query/response
+ *
+ * @prot: DOE Protocol
+ * @request_pl: The request payload
+ * @request_pl_sz: Size of the request payload (bytes)
+ * @response_pl: The response payload
+ * @response_pl_sz: Size of the response payload (bytes)
+ * @rv: Return value. Length of received response or error (bytes)
+ * @complete: Called when task is complete
+ * @private: Private data for the consumer
+ * @work: Used internally by the mailbox
+ * @doe_mb: Used internally by the mailbox
+ *
+ * The payload sizes and rv are specified in bytes with the following
+ * restrictions concerning the protocol.
+ *
+ * 1) The request_pl_sz must be a multiple of double words (4 bytes)
+ * 2) The response_pl_sz must be >= a single double word (4 bytes)
+ * 3) rv is returned as bytes but it will be a multiple of double words
+ *
+ * NOTE there is no need for the caller to initialize work or doe_mb.
+ */
+struct pci_doe_task {
+ struct pci_doe_protocol prot;
+ u32 *request_pl;
+ size_t request_pl_sz;
+ u32 *response_pl;
+ size_t response_pl_sz;
+ int rv;
+ void (*complete)(struct pci_doe_task *task);
+ void *private;
+
+ /* No need for the user to initialize these fields */
+ struct work_struct work;
+ struct pci_doe_mb *doe_mb;
+};
+
+/**
+ * pci_doe_for_each_off - Iterate each DOE capability
+ * @pdev: struct pci_dev to iterate
+ * @off: u16 of config space offset of each mailbox capability found
+ */
+#define pci_doe_for_each_off(pdev, off) \
+ for (off = pci_find_next_ext_capability(pdev, off, \
+ PCI_EXT_CAP_ID_DOE); \
+ off > 0; \
+ off = pci_find_next_ext_capability(pdev, off, \
+ PCI_EXT_CAP_ID_DOE))
+
+struct pci_doe_mb *pcim_doe_create_mb(struct pci_dev *pdev, u16 cap_offset);
+bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type);
+int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task);
+
+#endif
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 108f8523fa04..57b8e2ffb1dd 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -737,7 +737,8 @@
#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */
-#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT
+#define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */
+#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE
#define PCI_EXT_CAP_DSN_SIZEOF 12
#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
@@ -1103,4 +1104,30 @@
#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0
#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4
+/* Data Object Exchange */
+#define PCI_DOE_CAP 0x04 /* DOE Capabilities Register */
+#define PCI_DOE_CAP_INT_SUP 0x00000001 /* Interrupt Support */
+#define PCI_DOE_CAP_INT_MSG_NUM 0x00000ffe /* Interrupt Message Number */
+#define PCI_DOE_CTRL 0x08 /* DOE Control Register */
+#define PCI_DOE_CTRL_ABORT 0x00000001 /* DOE Abort */
+#define PCI_DOE_CTRL_INT_EN 0x00000002 /* DOE Interrupt Enable */
+#define PCI_DOE_CTRL_GO 0x80000000 /* DOE Go */
+#define PCI_DOE_STATUS 0x0c /* DOE Status Register */
+#define PCI_DOE_STATUS_BUSY 0x00000001 /* DOE Busy */
+#define PCI_DOE_STATUS_INT_STATUS 0x00000002 /* DOE Interrupt Status */
+#define PCI_DOE_STATUS_ERROR 0x00000004 /* DOE Error */
+#define PCI_DOE_STATUS_DATA_OBJECT_READY 0x80000000 /* Data Object Ready */
+#define PCI_DOE_WRITE 0x10 /* DOE Write Data Mailbox Register */
+#define PCI_DOE_READ 0x14 /* DOE Read Data Mailbox Register */
+
+/* DOE Data Object - note not actually registers */
+#define PCI_DOE_DATA_OBJECT_HEADER_1_VID 0x0000ffff
+#define PCI_DOE_DATA_OBJECT_HEADER_1_TYPE 0x00ff0000
+#define PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH 0x0003ffff
+
+#define PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX 0x000000ff
+#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID 0x0000ffff
+#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000
+#define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000
+
#endif /* LINUX_PCI_REGS_H */
--
2.35.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH V14 4/7] cxl/pci: Create PCI DOE mailbox's for memory devices
2022-07-15 3:04 [PATCH V14 0/7] CXL: Read CDAT ira.weiny
` (2 preceding siblings ...)
2022-07-15 3:04 ` [PATCH V14 3/7] PCI/DOE: Add DOE mailbox support functions ira.weiny
@ 2022-07-15 3:04 ` ira.weiny
2022-07-19 16:38 ` Jonathan Cameron
2022-07-15 3:04 ` [PATCH V14 5/7] driver-core: Introduce BIN_ATTR_ADMIN_{RO,RW} ira.weiny
` (3 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: ira.weiny @ 2022-07-15 3:04 UTC (permalink / raw)
To: Dan Williams, Bjorn Helgaas, Jonathan Cameron
Cc: Ira Weiny, Davidlohr Bueso, Lukas Wunner, Alison Schofield,
Vishal Verma, Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl,
linux-pci
From: Ira Weiny <ira.weiny@intel.com>
DOE mailbox objects will be needed for various mailbox communications
with each memory device.
Iterate each DOE mailbox capability and create PCI DOE mailbox objects
as found.
It is not anticipated that this is the final resting place for the
iteration of the DOE devices. The support of switch ports will drive
this code into the PCIe side. In this imagined architecture the CXL
port driver would then query into the PCI device for the DOE mailbox
array.
For now creating the mailboxes in the CXL port is good enough for the
endpoints. Later PCIe ports will need to support this to support switch
ports more generically.
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
---
Changes from V13:
Dan:
s/pci_err/dev_err
s/pci_dbg/dev_dbg
Move xa_init() into devm_cxl_pci_create_doe()
Changes from V12:
remove irq param from CXL
Jonathan:
remove xa local variable
clarify MB creation as best effort
But ensure pci_err() if they fail
Check devm_add_action() return for failure
Davidlohr and Jonathan:
Return error ...
Changes from V11:
Drop review from: Ben Widawsky <bwidawsk@kernel.org>
Remove irq code for now
Adjust for pci_doe_get_int_msg_num()
Adjust for pcim_doe_create_mb()
(No longer need to handle the destroy.)
Use xarray for DOE mailbox array
Changes from V9:
Bug fix: ensure DOE mailboxes are iterated before memdev add
Ben Widawsky
Set use_irq to false and just return on error.
Don't return a value from devm_cxl_pci_create_doe()
Skip allocating doe_mb array if there are no mailboxes
Skip requesting irqs if none found.
Ben/Jonathan Cameron
s/num_irqs/max_irqs
Changes from V8:
Move PCI_DOE selection to CXL_BUS to support future patches
which move queries into the port code.
Remove Auxiliary device arch
Squash the functionality of the auxiliary driver into this
patch.
Split out the irq handling a bit.
Changes from V7:
Minor code clean ups
Rebased on cxl-pending
Changes from V6:
Move all the auxiliary device stuff to the CXL layer
Changes from V5:
Split the CXL specific stuff off from the PCI DOE create
auxiliary device code.
---
drivers/cxl/Kconfig | 1 +
drivers/cxl/cxlmem.h | 3 +++
drivers/cxl/pci.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 48 insertions(+)
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index f64e3984689f..7adaaf80b302 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -2,6 +2,7 @@
menuconfig CXL_BUS
tristate "CXL (Compute Express Link) Devices Support"
depends on PCI
+ select PCI_DOE
help
CXL is a bus that is electrically compatible with PCI Express, but
layers three protocols on that signalling (CXL.io, CXL.cache, and
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index c6d6f57856cc..bfa2eaf649a9 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -192,6 +192,7 @@ struct cxl_endpoint_dvsec_info {
* @component_reg_phys: register base of component registers
* @info: Cached DVSEC information about the device.
* @serial: PCIe Device Serial Number
+ * @doe_mbs: PCI DOE mailbox array
* @mbox_send: @dev specific transport for transmitting mailbox commands
*
* See section 8.2.9.5.2 Capacity Configuration and Label Storage for
@@ -226,6 +227,8 @@ struct cxl_dev_state {
resource_size_t component_reg_phys;
u64 serial;
+ struct xarray doe_mbs;
+
int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
};
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index eeff9599acda..faeb5d9d7a7a 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -8,6 +8,7 @@
#include <linux/mutex.h>
#include <linux/list.h>
#include <linux/pci.h>
+#include <linux/pci-doe.h>
#include <linux/io.h>
#include "cxlmem.h"
#include "cxlpci.h"
@@ -386,6 +387,47 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
return rc;
}
+static void cxl_pci_destroy_doe(void *mbs)
+{
+ xa_destroy(mbs);
+}
+
+static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds)
+{
+ struct device *dev = cxlds->dev;
+ struct pci_dev *pdev = to_pci_dev(dev);
+ u16 off = 0;
+
+ xa_init(&cxlds->doe_mbs);
+ if (devm_add_action(&pdev->dev, cxl_pci_destroy_doe, &cxlds->doe_mbs)) {
+ dev_err(dev, "Failed to create XArray for DOE's\n");
+ return;
+ }
+
+ /*
+ * Mailbox creation is best effort. Higher layers must determine if
+ * the lack of a mailbox for their protocol is a device failure or not.
+ */
+ pci_doe_for_each_off(pdev, off) {
+ struct pci_doe_mb *doe_mb;
+
+ doe_mb = pcim_doe_create_mb(pdev, off);
+ if (IS_ERR(doe_mb)) {
+ dev_err(dev, "Failed to create MB object for MB @ %x\n",
+ off);
+ continue;
+ }
+
+ if (xa_insert(&cxlds->doe_mbs, off, doe_mb, GFP_KERNEL)) {
+ dev_err(dev, "xa_insert failed to insert MB @ %x\n",
+ off);
+ continue;
+ }
+
+ dev_dbg(dev, "Created DOE mailbox @%x\n", off);
+ }
+}
+
static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct cxl_register_map map;
@@ -434,6 +476,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
cxlds->component_reg_phys = cxl_regmap_to_base(pdev, &map);
+ devm_cxl_pci_create_doe(cxlds);
+
rc = cxl_pci_setup_mailbox(cxlds);
if (rc)
return rc;
--
2.35.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH V14 5/7] driver-core: Introduce BIN_ATTR_ADMIN_{RO,RW}
2022-07-15 3:04 [PATCH V14 0/7] CXL: Read CDAT ira.weiny
` (3 preceding siblings ...)
2022-07-15 3:04 ` [PATCH V14 4/7] cxl/pci: Create PCI DOE mailbox's for memory devices ira.weiny
@ 2022-07-15 3:04 ` ira.weiny
2022-07-19 16:39 ` Jonathan Cameron
2022-07-15 3:04 ` [PATCH V14 6/7] cxl/port: Read CDAT table ira.weiny
` (2 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: ira.weiny @ 2022-07-15 3:04 UTC (permalink / raw)
To: Dan Williams, Bjorn Helgaas, Jonathan Cameron
Cc: Ira Weiny, Krzysztof Wilczyński, Greg Kroah-Hartman,
Lukas Wunner, Alison Schofield, Vishal Verma, Dave Jiang,
Ben Widawsky, linux-kernel, linux-cxl, linux-pci
From: Ira Weiny <ira.weiny@intel.com>
Many binary attributes need to limit access to CAP_SYS_ADMIN only; ie
many binary attributes specify is_visible with 0400 or 0600.
Make setting the permissions of such attributes more explicit by
defining BIN_ATTR_ADMIN_{RO,RW}.
Cc: Bjorn Helgaas <bhelgaas@google.com>
Suggested-by: Dan Williams <dan.j.williams@intel.com>
Suggested-by: Krzysztof Wilczyński <kw@linux.com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
---
Changes from V12:
Pick up review tag
Bjorn:
NOTE: this has a lot of similarities to
https://lore.kernel.org/all/20210416205856.3234481-7-kw@linux.com/
I'm not sure why that patch was not picked up. But I've
added Krzysztof as a suggested by if that is ok?
Changes from V11:
New Patch
---
include/linux/sysfs.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/include/linux/sysfs.h b/include/linux/sysfs.h
index e3f1e8ac1f85..fd3fe5c8c17f 100644
--- a/include/linux/sysfs.h
+++ b/include/linux/sysfs.h
@@ -235,6 +235,22 @@ struct bin_attribute bin_attr_##_name = __BIN_ATTR_WO(_name, _size)
#define BIN_ATTR_RW(_name, _size) \
struct bin_attribute bin_attr_##_name = __BIN_ATTR_RW(_name, _size)
+
+#define __BIN_ATTR_ADMIN_RO(_name, _size) { \
+ .attr = { .name = __stringify(_name), .mode = 0400 }, \
+ .read = _name##_read, \
+ .size = _size, \
+}
+
+#define __BIN_ATTR_ADMIN_RW(_name, _size) \
+ __BIN_ATTR(_name, 0600, _name##_read, _name##_write, _size)
+
+#define BIN_ATTR_ADMIN_RO(_name, _size) \
+struct bin_attribute bin_attr_##_name = __BIN_ATTR_ADMIN_RO(_name, _size)
+
+#define BIN_ATTR_ADMIN_RW(_name, _size) \
+struct bin_attribute bin_attr_##_name = __BIN_ATTR_ADMIN_RW(_name, _size)
+
struct sysfs_ops {
ssize_t (*show)(struct kobject *, struct attribute *, char *);
ssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t);
--
2.35.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH V14 6/7] cxl/port: Read CDAT table
2022-07-15 3:04 [PATCH V14 0/7] CXL: Read CDAT ira.weiny
` (4 preceding siblings ...)
2022-07-15 3:04 ` [PATCH V14 5/7] driver-core: Introduce BIN_ATTR_ADMIN_{RO,RW} ira.weiny
@ 2022-07-15 3:04 ` ira.weiny
2022-07-16 3:27 ` Dan Williams
2022-07-19 1:19 ` Dan Williams
2022-07-15 3:04 ` [PATCH V14 7/7] cxl/port: Introduce cxl_cdat_valid() ira.weiny
2022-07-19 15:21 ` [PATCH V14 0/7] CXL: Read CDAT Jonathan Cameron
7 siblings, 2 replies; 20+ messages in thread
From: ira.weiny @ 2022-07-15 3:04 UTC (permalink / raw)
To: Dan Williams, Bjorn Helgaas, Jonathan Cameron
Cc: Ira Weiny, Lukas Wunner, Alison Schofield, Vishal Verma,
Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl, linux-pci
From: Ira Weiny <ira.weiny@intel.com>
The OS will need CDAT data from CXL devices to properly set up
interleave sets. Currently this is supported through a DOE mailbox
which supports CDAT.
Search the DOE mailboxes available, query CDAT data, and cache the data
for later parsing.
Provide a sysfs binary attribute to allow dumping of the CDAT.
Binary dumping is modeled on /sys/firmware/ACPI/tables/
The ability to dump this table will be very useful for emulation of real
devices once they become available as QEMU CXL type 3 device emulation will
be able to load this file in.
This does not support table updates at runtime. It will always provide
whatever was there when first cached. Handling of table updates can be
implemented later.
Finally create a complete list of CDAT defines within cdat.h for code
wishing to decode the CDAT table.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
---
Changes from V13:
Dan:
Add entry in Documentation/ABI/testing/sysfs-bus-cxl
Remove table parsing defines.
s/cdat_sup/cdat_available
s/cdat_mb/cdat_doe/
Don't check endpoint in find_cdat_doe()
Create CDAT_DOE_TASK macro
Changes from V12:
Fix checking for task.rv for errors
Ensure no over run of non-DW aligned buffer length's
Changes from V11:
Adjust for the use of DOE mailbox xarray
Dan Williams:
Remove unnecessary get/put device
Use new BIN_ATTR_ADMIN_RO macro
Flag that CDAT was supported
If there is a read error then the CDAT sysfs
will return a 0 length entry
Changes from V10:
Ben Widawsky
Failure to find CDAT should be a debug message not error
Remove reference to cdat_mb from the port object
Dropped [PATCH V10 5/9] cxl/port: Find a DOE mailbox which supports
CDAT
Iterate the mailboxes for the CDAT one each time.
Define CXL_DOE_TABLE_ACCESS_LAST_ENTRY and add comment about
it's use.
Changes from V9:
Add debugging output
Jonathan Cameron
Move read_cdat to port probe by using dev_groups for the
sysfs attributes. This avoids issues with using devm
before the driver is loaded while making sure the CDAT
binary is available.
Changes from V8:
Fix length print format
Incorporate feedback from Jonathan
Move all this to cxl_port which can help support switches when
the time comes.
Changes from V6:
Fix issue with devm use
Move cached cdat data to cxl_dev_state
Use new pci_doe_submit_task()
Ensure the aux driver is locked while processing tasks
Rebased on cxl-pending
Changes from V5:
Add proper guards around cdat.h
Split out finding the CDAT DOE mailbox
Use cxl_cdat to group CDAT data together
Adjust to use auxiliary_find_device() to find the DOE device
which supplies the CDAT protocol.
Rebased to latest
Remove dev_dbg(length)
Remove unneeded DOE Table access defines
Move CXL_DOE_PROTOCOL_TABLE_ACCESS define into this patch where
it is used
Changes from V4:
Split this into it's own patch
Rearchitect this such that the memdev driver calls into the DOE
driver via the cxl_mem state object. This allows CDAT data to
come from any type of cxl_mem object not just PCI DOE.
Rebase on new struct cxl_dev_state
---
Documentation/ABI/testing/sysfs-bus-cxl | 10 ++
drivers/cxl/cdat.h | 61 +++++++++
drivers/cxl/core/pci.c | 169 ++++++++++++++++++++++++
drivers/cxl/cxl.h | 5 +
drivers/cxl/cxlpci.h | 1 +
drivers/cxl/port.c | 54 ++++++++
6 files changed, 300 insertions(+)
create mode 100644 drivers/cxl/cdat.h
diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
index 1fd5984b6158..6fb6459466f8 100644
--- a/Documentation/ABI/testing/sysfs-bus-cxl
+++ b/Documentation/ABI/testing/sysfs-bus-cxl
@@ -164,3 +164,13 @@ Description:
expander memory (type-3). The 'target_type' attribute indicates
the current setting which may dynamically change based on what
memory regions are activated in this decode hierarchy.
+
+What: /sys/bus/cxl/devices/endpointX/CDAT/cdat
+Date: July, 2022
+KernelVersion: v5.19
+Contact: linux-cxl@vger.kernel.org
+Description:
+ (RO) If this sysfs entry is not present no DOE mailbox was
+ found to support CDAT data. If it is present and the length of
+ the data is 0 reading the CDAT data failed. Otherwise the CDAT
+ data is reported.
diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h
new file mode 100644
index 000000000000..67010717ffca
--- /dev/null
+++ b/drivers/cxl/cdat.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CXL_CDAT_H__
+#define __CXL_CDAT_H__
+
+/*
+ * Coherent Device Attribute table (CDAT)
+ *
+ * Specification available from UEFI.org
+ *
+ * Whilst CDAT is defined as a single table, the access via DOE maiboxes is
+ * done one entry at a time, where the first entry is the header.
+ */
+
+#define CXL_DOE_TABLE_ACCESS_REQ_CODE 0x000000ff
+#define CXL_DOE_TABLE_ACCESS_REQ_CODE_READ 0
+#define CXL_DOE_TABLE_ACCESS_TABLE_TYPE 0x0000ff00
+#define CXL_DOE_TABLE_ACCESS_TABLE_TYPE_CDATA 0
+#define CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE 0xffff0000
+#define CXL_DOE_TABLE_ACCESS_LAST_ENTRY 0xffff
+
+/*
+ * CDAT entries are little endian and are read from PCI config space which
+ * is also little endian.
+ * As such, on a big endian system these will have been reversed.
+ * This prevents us from making easy use of packed structures.
+ * Style form pci_regs.h
+ */
+
+#define CDAT_HEADER_LENGTH_DW 4
+#define CDAT_HEADER_LENGTH_BYTES (CDAT_HEADER_LENGTH_DW * sizeof(u32))
+#define CDAT_HEADER_DW0_LENGTH 0xffffffff
+#define CDAT_HEADER_DW1_REVISION 0x000000ff
+#define CDAT_HEADER_DW1_CHECKSUM 0x0000ff00
+/* CDAT_HEADER_DW2_RESERVED */
+#define CDAT_HEADER_DW3_SEQUENCE 0xffffffff
+
+/* All structures have a common first DW */
+#define CDAT_STRUCTURE_DW0_TYPE 0x000000ff
+#define CDAT_STRUCTURE_DW0_TYPE_DSMAS 0
+#define CDAT_STRUCTURE_DW0_TYPE_DSLBIS 1
+#define CDAT_STRUCTURE_DW0_TYPE_DSMSCIS 2
+#define CDAT_STRUCTURE_DW0_TYPE_DSIS 3
+#define CDAT_STRUCTURE_DW0_TYPE_DSEMTS 4
+#define CDAT_STRUCTURE_DW0_TYPE_SSLBIS 5
+
+#define CDAT_STRUCTURE_DW0_LENGTH 0xffff0000
+
+#define CXL_DOE_PROTOCOL_TABLE_ACCESS 2
+
+/**
+ * struct cxl_cdat - CXL CDAT data
+ *
+ * @table: cache of CDAT table
+ * @length: length of cached CDAT table
+ */
+struct cxl_cdat {
+ void *table;
+ size_t length;
+};
+
+#endif /* !__CXL_CDAT_H__ */
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 7672789c3225..dd5d1da412ca 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -4,10 +4,12 @@
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/pci.h>
+#include <linux/pci-doe.h>
#include <cxlpci.h>
#include <cxlmem.h>
#include <cxl.h>
#include "core.h"
+#include "cdat.h"
/**
* DOC: cxl core pci
@@ -452,3 +454,170 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm)
return 0;
}
EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);
+
+static struct pci_doe_mb *find_cdat_doe(struct device *uport)
+{
+ struct cxl_memdev *cxlmd;
+ struct cxl_dev_state *cxlds;
+ unsigned long index;
+ void *entry;
+
+ cxlmd = to_cxl_memdev(uport);
+ cxlds = cxlmd->cxlds;
+
+ xa_for_each(&cxlds->doe_mbs, index, entry) {
+ struct pci_doe_mb *cur = entry;
+
+ if (pci_doe_supports_prot(cur, PCI_DVSEC_VENDOR_ID_CXL,
+ CXL_DOE_PROTOCOL_TABLE_ACCESS))
+ return cur;
+ }
+
+ return NULL;
+}
+
+#define CDAT_DOE_REQ(entry_handle) \
+ (FIELD_PREP(CXL_DOE_TABLE_ACCESS_REQ_CODE, \
+ CXL_DOE_TABLE_ACCESS_REQ_CODE_READ) | \
+ FIELD_PREP(CXL_DOE_TABLE_ACCESS_TABLE_TYPE, \
+ CXL_DOE_TABLE_ACCESS_TABLE_TYPE_CDATA) | \
+ FIELD_PREP(CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE, (entry_handle)))
+
+static void cxl_doe_task_complete(struct pci_doe_task *task)
+{
+ complete(task->private);
+}
+
+#define CDAT_DOE_TASK(req, req_sz, rsp, rsp_sz, comp) \
+{ \
+ .prot.vid = PCI_DVSEC_VENDOR_ID_CXL, \
+ .prot.type = CXL_DOE_PROTOCOL_TABLE_ACCESS, \
+ .request_pl = req, \
+ .request_pl_sz = req_sz, \
+ .response_pl = rsp, \
+ .response_pl_sz = rsp_sz, \
+ .complete = cxl_doe_task_complete, \
+ .private = comp, \
+}
+
+static int cxl_cdat_get_length(struct device *dev,
+ struct pci_doe_mb *cdat_doe,
+ size_t *length)
+{
+ u32 cdat_request_pl = CDAT_DOE_REQ(0);
+ u32 cdat_response_pl[32];
+ DECLARE_COMPLETION_ONSTACK(c);
+ struct pci_doe_task task = CDAT_DOE_TASK(&cdat_request_pl,
+ sizeof(cdat_request_pl),
+ cdat_response_pl,
+ sizeof(cdat_response_pl),
+ &c);
+ int rc;
+
+ rc = pci_doe_submit_task(cdat_doe, &task);
+ if (rc < 0) {
+ dev_err(dev, "DOE submit failed: %d", rc);
+ return rc;
+ }
+ wait_for_completion(&c);
+ if (task.rv < sizeof(u32))
+ return -EIO;
+
+ *length = cdat_response_pl[1];
+ dev_dbg(dev, "CDAT length %zu\n", *length);
+
+ return 0;
+}
+
+static int cxl_cdat_read_table(struct device *dev,
+ struct pci_doe_mb *cdat_doe,
+ struct cxl_cdat *cdat)
+{
+ size_t length = cdat->length;
+ u32 *data = cdat->table;
+ int entry_handle = 0;
+
+ do {
+ u32 cdat_request_pl = CDAT_DOE_REQ(entry_handle);
+ u32 cdat_response_pl[32];
+ DECLARE_COMPLETION_ONSTACK(c);
+ struct pci_doe_task task = CDAT_DOE_TASK(&cdat_request_pl,
+ sizeof(cdat_request_pl),
+ cdat_response_pl,
+ sizeof(cdat_response_pl),
+ &c);
+ size_t entry_dw;
+ u32 *entry;
+ int rc;
+
+ rc = pci_doe_submit_task(cdat_doe, &task);
+ if (rc < 0) {
+ dev_err(dev, "DOE submit failed: %d", rc);
+ return rc;
+ }
+ wait_for_completion(&c);
+ /* 1 DW header + 1 DW data min */
+ if (task.rv < (2 * sizeof(u32)))
+ return -EIO;
+
+ /* Get the CXL table access header entry handle */
+ entry_handle = FIELD_GET(CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE,
+ cdat_response_pl[0]);
+ entry = cdat_response_pl + 1;
+ entry_dw = task.rv / sizeof(u32);
+ /* Skip Header */
+ entry_dw -= 1;
+ entry_dw = min(length / sizeof(u32), entry_dw);
+ /* Prevent length < 1 DW from causing a buffer overflow */
+ if (entry_dw) {
+ memcpy(data, entry, entry_dw * sizeof(u32));
+ length -= entry_dw * sizeof(u32);
+ data += entry_dw;
+ }
+ } while (entry_handle != CXL_DOE_TABLE_ACCESS_LAST_ENTRY);
+
+ return 0;
+}
+
+/**
+ * read_cdat_data - Read the CDAT data on this port
+ * @port: Port to read data from
+ *
+ * This call will sleep waiting for responses from the DOE mailbox.
+ */
+void read_cdat_data(struct cxl_port *port)
+{
+ static struct pci_doe_mb *cdat_doe;
+ struct device *dev = &port->dev;
+ struct device *uport = port->uport;
+ size_t cdat_length;
+ int rc;
+
+ cdat_doe = find_cdat_doe(uport);
+ if (!cdat_doe) {
+ dev_dbg(dev, "No CDAT mailbox\n");
+ return;
+ }
+
+ port->cdat_available = true;
+
+ if (cxl_cdat_get_length(dev, cdat_doe, &cdat_length)) {
+ dev_dbg(dev, "No CDAT length\n");
+ return;
+ }
+
+ port->cdat.table = devm_kzalloc(dev, cdat_length, GFP_KERNEL);
+ if (!port->cdat.table)
+ return;
+
+ port->cdat.length = cdat_length;
+ rc = cxl_cdat_read_table(dev, cdat_doe, &port->cdat);
+ if (rc) {
+ /* Don't leave table data allocated on error */
+ devm_kfree(dev, port->cdat.table);
+ port->cdat.table = NULL;
+ port->cdat.length = 0;
+ dev_err(dev, "CDAT data read error\n");
+ }
+}
+EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 570bd9f8141b..64ea8c80b917 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -8,6 +8,7 @@
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/io.h>
+#include "cdat.h"
/**
* DOC: cxl objects
@@ -289,6 +290,8 @@ struct cxl_nvdimm {
* @component_reg_phys: component register capability base address (optional)
* @dead: last ep has been removed, force port re-creation
* @depth: How deep this port is relative to the root. depth 0 is the root.
+ * @cdat: Cached CDAT data
+ * @cdat_available: Should a CDAT attribute be available in sysfs
*/
struct cxl_port {
struct device dev;
@@ -301,6 +304,8 @@ struct cxl_port {
resource_size_t component_reg_phys;
bool dead;
unsigned int depth;
+ struct cxl_cdat cdat;
+ bool cdat_available;
};
/**
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index fce1c11729c2..eec597dbe763 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -74,4 +74,5 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
int devm_cxl_port_enumerate_dports(struct cxl_port *port);
struct cxl_dev_state;
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
+void read_cdat_data(struct cxl_port *port);
#endif /* __CXL_PCI_H__ */
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 3cf308f114c4..08b8ac76f87b 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -53,6 +53,9 @@ static int cxl_port_probe(struct device *dev)
struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport);
struct cxl_dev_state *cxlds = cxlmd->cxlds;
+ /* Cache the data early to ensure is_visible() works */
+ read_cdat_data(port);
+
get_device(&cxlmd->dev);
rc = devm_add_action_or_reset(dev, schedule_detach, cxlmd);
if (rc)
@@ -78,10 +81,61 @@ static int cxl_port_probe(struct device *dev)
return 0;
}
+static ssize_t cdat_read(struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr, char *buf,
+ loff_t offset, size_t count)
+{
+ struct device *dev = kobj_to_dev(kobj);
+ struct cxl_port *port = to_cxl_port(dev);
+
+ if (!port->cdat_available)
+ return -ENXIO;
+
+ if (!port->cdat.table)
+ return 0;
+
+ return memory_read_from_buffer(buf, count, &offset,
+ port->cdat.table,
+ port->cdat.length);
+}
+
+static BIN_ATTR_ADMIN_RO(cdat, 0);
+
+static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj,
+ struct bin_attribute *attr, int i)
+{
+ struct device *dev = kobj_to_dev(kobj);
+ struct cxl_port *port = to_cxl_port(dev);
+
+ if ((attr == &bin_attr_cdat) && port->cdat_available)
+ return attr->attr.mode;
+
+ return 0;
+}
+
+static struct bin_attribute *cxl_cdat_bin_attributes[] = {
+ &bin_attr_cdat,
+ NULL,
+};
+
+static struct attribute_group cxl_cdat_attribute_group = {
+ .name = "CDAT",
+ .bin_attrs = cxl_cdat_bin_attributes,
+ .is_bin_visible = cxl_port_bin_attr_is_visible,
+};
+
+static const struct attribute_group *cxl_port_attribute_groups[] = {
+ &cxl_cdat_attribute_group,
+ NULL,
+};
+
static struct cxl_driver cxl_port_driver = {
.name = "cxl_port",
.probe = cxl_port_probe,
.id = CXL_DEVICE_PORT,
+ .drv = {
+ .dev_groups = cxl_port_attribute_groups,
+ },
};
module_cxl_driver(cxl_port_driver);
--
2.35.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH V14 7/7] cxl/port: Introduce cxl_cdat_valid()
2022-07-15 3:04 [PATCH V14 0/7] CXL: Read CDAT ira.weiny
` (5 preceding siblings ...)
2022-07-15 3:04 ` [PATCH V14 6/7] cxl/port: Read CDAT table ira.weiny
@ 2022-07-15 3:04 ` ira.weiny
2022-07-16 2:26 ` Dan Williams
2022-07-19 15:21 ` [PATCH V14 0/7] CXL: Read CDAT Jonathan Cameron
7 siblings, 1 reply; 20+ messages in thread
From: ira.weiny @ 2022-07-15 3:04 UTC (permalink / raw)
To: Dan Williams, Bjorn Helgaas, Jonathan Cameron
Cc: Ira Weiny, Lukas Wunner, Alison Schofield, Vishal Verma,
Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl, linux-pci
From: Ira Weiny <ira.weiny@intel.com>
The CDAT data is protected by a checksum and should be the proper
length.
Introduce cxl_cdat_valid() to validate the data. While at it check and
store the sequence number.
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
---
Changes from V12
Jonathan:
Remove unneeded rc check.
Changes from V8
Move code to cxl/core/pci.c
Changes from V6
Change name to cxl_cdat_valid() as this validates all the CDAT
data not just the header
Add error and debug prints
Changes from V5
New patch, split out
Update cdat_hdr_valid()
Remove revision and cs field parsing
There is no point in these
Add seq check and debug print.
---
drivers/cxl/cdat.h | 2 ++
drivers/cxl/core/pci.c | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h
index 67010717ffca..162ef474ee5a 100644
--- a/drivers/cxl/cdat.h
+++ b/drivers/cxl/cdat.h
@@ -52,10 +52,12 @@
*
* @table: cache of CDAT table
* @length: length of cached CDAT table
+ * @seq: Last read Sequence number of the CDAT table
*/
struct cxl_cdat {
void *table;
size_t length;
+ u32 seq;
};
#endif /* !__CXL_CDAT_H__ */
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index dd5d1da412ca..36e14549997d 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -529,6 +529,40 @@ static int cxl_cdat_get_length(struct device *dev,
return 0;
}
+static bool cxl_cdat_valid(struct device *dev, struct cxl_cdat *cdat)
+{
+ u32 *table = cdat->table;
+ u8 *data8 = cdat->table;
+ u32 length, seq;
+ u8 check;
+ int i;
+
+ length = FIELD_GET(CDAT_HEADER_DW0_LENGTH, table[0]);
+ if ((length < CDAT_HEADER_LENGTH_BYTES) || (length > cdat->length)) {
+ dev_err(dev, "CDAT Invalid length %u (%zu-%zu)\n", length,
+ CDAT_HEADER_LENGTH_BYTES, cdat->length);
+ return false;
+ }
+
+ for (check = 0, i = 0; i < length; i++)
+ check += data8[i];
+
+ dev_dbg(dev, "CDAT length %u CS %u\n", length, check);
+ if (check != 0) {
+ dev_err(dev, "CDAT Invalid checksum %u\n", check);
+ return false;
+ }
+
+ seq = FIELD_GET(CDAT_HEADER_DW3_SEQUENCE, table[3]);
+ /* Store the sequence for now. */
+ if (cdat->seq != seq) {
+ dev_info(dev, "CDAT seq change %x -> %x\n", cdat->seq, seq);
+ cdat->seq = seq;
+ }
+
+ return true;
+}
+
static int cxl_cdat_read_table(struct device *dev,
struct pci_doe_mb *cdat_doe,
struct cxl_cdat *cdat)
@@ -576,6 +610,9 @@ static int cxl_cdat_read_table(struct device *dev,
}
} while (entry_handle != CXL_DOE_TABLE_ACCESS_LAST_ENTRY);
+ if (!cxl_cdat_valid(dev, cdat))
+ return -EIO;
+
return 0;
}
--
2.35.3
^ permalink raw reply related [flat|nested] 20+ messages in thread
* RE: [PATCH V14 7/7] cxl/port: Introduce cxl_cdat_valid()
2022-07-15 3:04 ` [PATCH V14 7/7] cxl/port: Introduce cxl_cdat_valid() ira.weiny
@ 2022-07-16 2:26 ` Dan Williams
2022-07-19 16:47 ` Jonathan Cameron
0 siblings, 1 reply; 20+ messages in thread
From: Dan Williams @ 2022-07-16 2:26 UTC (permalink / raw)
To: ira.weiny, Dan Williams, Bjorn Helgaas, Jonathan Cameron
Cc: Ira Weiny, Lukas Wunner, Alison Schofield, Vishal Verma,
Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl, linux-pci
ira.weiny@ wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> The CDAT data is protected by a checksum and should be the proper
> length.
>
> Introduce cxl_cdat_valid() to validate the data. While at it check and
> store the sequence number.
I am going to drop this one. Userspace can determine validity when it
parses it. When the kernel grows a CDAT parser it will rely on the
standard validation of ACPI-table-like structures from a future
__acpi_table_parse_entries() derivative for this purpose.
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH V14 6/7] cxl/port: Read CDAT table
2022-07-15 3:04 ` [PATCH V14 6/7] cxl/port: Read CDAT table ira.weiny
@ 2022-07-16 3:27 ` Dan Williams
2022-07-19 1:19 ` Dan Williams
1 sibling, 0 replies; 20+ messages in thread
From: Dan Williams @ 2022-07-16 3:27 UTC (permalink / raw)
To: ira.weiny, Dan Williams, Bjorn Helgaas, Jonathan Cameron
Cc: Ira Weiny, Lukas Wunner, Alison Schofield, Vishal Verma,
Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl, linux-pci
ira.weiny@ wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> The OS will need CDAT data from CXL devices to properly set up
> interleave sets. Currently this is supported through a DOE mailbox
> which supports CDAT.
>
> Search the DOE mailboxes available, query CDAT data, and cache the data
> for later parsing.
>
> Provide a sysfs binary attribute to allow dumping of the CDAT.
>
> Binary dumping is modeled on /sys/firmware/ACPI/tables/
>
> The ability to dump this table will be very useful for emulation of real
> devices once they become available as QEMU CXL type 3 device emulation will
> be able to load this file in.
>
> This does not support table updates at runtime. It will always provide
> whatever was there when first cached. Handling of table updates can be
> implemented later.
>
> Finally create a complete list of CDAT defines within cdat.h for code
> wishing to decode the CDAT table.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
>
> ---
> Changes from V13:
> Dan:
> Add entry in Documentation/ABI/testing/sysfs-bus-cxl
> Remove table parsing defines.
> s/cdat_sup/cdat_available
> s/cdat_mb/cdat_doe/
> Don't check endpoint in find_cdat_doe()
> Create CDAT_DOE_TASK macro
>
> Changes from V12:
> Fix checking for task.rv for errors
> Ensure no over run of non-DW aligned buffer length's
>
> Changes from V11:
> Adjust for the use of DOE mailbox xarray
> Dan Williams:
> Remove unnecessary get/put device
> Use new BIN_ATTR_ADMIN_RO macro
> Flag that CDAT was supported
> If there is a read error then the CDAT sysfs
> will return a 0 length entry
>
> Changes from V10:
> Ben Widawsky
> Failure to find CDAT should be a debug message not error
> Remove reference to cdat_mb from the port object
> Dropped [PATCH V10 5/9] cxl/port: Find a DOE mailbox which supports
> CDAT
> Iterate the mailboxes for the CDAT one each time.
> Define CXL_DOE_TABLE_ACCESS_LAST_ENTRY and add comment about
> it's use.
>
> Changes from V9:
> Add debugging output
> Jonathan Cameron
> Move read_cdat to port probe by using dev_groups for the
> sysfs attributes. This avoids issues with using devm
> before the driver is loaded while making sure the CDAT
> binary is available.
>
> Changes from V8:
> Fix length print format
> Incorporate feedback from Jonathan
> Move all this to cxl_port which can help support switches when
> the time comes.
>
> Changes from V6:
> Fix issue with devm use
> Move cached cdat data to cxl_dev_state
> Use new pci_doe_submit_task()
> Ensure the aux driver is locked while processing tasks
> Rebased on cxl-pending
>
> Changes from V5:
> Add proper guards around cdat.h
> Split out finding the CDAT DOE mailbox
> Use cxl_cdat to group CDAT data together
> Adjust to use auxiliary_find_device() to find the DOE device
> which supplies the CDAT protocol.
> Rebased to latest
> Remove dev_dbg(length)
> Remove unneeded DOE Table access defines
> Move CXL_DOE_PROTOCOL_TABLE_ACCESS define into this patch where
> it is used
>
> Changes from V4:
> Split this into it's own patch
> Rearchitect this such that the memdev driver calls into the DOE
> driver via the cxl_mem state object. This allows CDAT data to
> come from any type of cxl_mem object not just PCI DOE.
> Rebase on new struct cxl_dev_state
> ---
> Documentation/ABI/testing/sysfs-bus-cxl | 10 ++
> drivers/cxl/cdat.h | 61 +++++++++
> drivers/cxl/core/pci.c | 169 ++++++++++++++++++++++++
> drivers/cxl/cxl.h | 5 +
> drivers/cxl/cxlpci.h | 1 +
> drivers/cxl/port.c | 54 ++++++++
> 6 files changed, 300 insertions(+)
> create mode 100644 drivers/cxl/cdat.h
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
> index 1fd5984b6158..6fb6459466f8 100644
> --- a/Documentation/ABI/testing/sysfs-bus-cxl
> +++ b/Documentation/ABI/testing/sysfs-bus-cxl
> @@ -164,3 +164,13 @@ Description:
> expander memory (type-3). The 'target_type' attribute indicates
> the current setting which may dynamically change based on what
> memory regions are activated in this decode hierarchy.
> +
> +What: /sys/bus/cxl/devices/endpointX/CDAT/cdat
> +Date: July, 2022
> +KernelVersion: v5.19
> +Contact: linux-cxl@vger.kernel.org
> +Description:
> + (RO) If this sysfs entry is not present no DOE mailbox was
> + found to support CDAT data. If it is present and the length of
> + the data is 0 reading the CDAT data failed. Otherwise the CDAT
> + data is reported.
> diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h
> new file mode 100644
> index 000000000000..67010717ffca
> --- /dev/null
> +++ b/drivers/cxl/cdat.h
> @@ -0,0 +1,61 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __CXL_CDAT_H__
> +#define __CXL_CDAT_H__
> +
> +/*
> + * Coherent Device Attribute table (CDAT)
> + *
> + * Specification available from UEFI.org
> + *
> + * Whilst CDAT is defined as a single table, the access via DOE maiboxes is
> + * done one entry at a time, where the first entry is the header.
> + */
> +
> +#define CXL_DOE_TABLE_ACCESS_REQ_CODE 0x000000ff
> +#define CXL_DOE_TABLE_ACCESS_REQ_CODE_READ 0
> +#define CXL_DOE_TABLE_ACCESS_TABLE_TYPE 0x0000ff00
> +#define CXL_DOE_TABLE_ACCESS_TABLE_TYPE_CDATA 0
> +#define CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE 0xffff0000
> +#define CXL_DOE_TABLE_ACCESS_LAST_ENTRY 0xffff
> +
> +/*
> + * CDAT entries are little endian and are read from PCI config space which
> + * is also little endian.
> + * As such, on a big endian system these will have been reversed.
> + * This prevents us from making easy use of packed structures.
> + * Style form pci_regs.h
> + */
> +
> +#define CDAT_HEADER_LENGTH_DW 4
> +#define CDAT_HEADER_LENGTH_BYTES (CDAT_HEADER_LENGTH_DW * sizeof(u32))
> +#define CDAT_HEADER_DW0_LENGTH 0xffffffff
> +#define CDAT_HEADER_DW1_REVISION 0x000000ff
> +#define CDAT_HEADER_DW1_CHECKSUM 0x0000ff00
> +/* CDAT_HEADER_DW2_RESERVED */
> +#define CDAT_HEADER_DW3_SEQUENCE 0xffffffff
> +
> +/* All structures have a common first DW */
> +#define CDAT_STRUCTURE_DW0_TYPE 0x000000ff
> +#define CDAT_STRUCTURE_DW0_TYPE_DSMAS 0
> +#define CDAT_STRUCTURE_DW0_TYPE_DSLBIS 1
> +#define CDAT_STRUCTURE_DW0_TYPE_DSMSCIS 2
> +#define CDAT_STRUCTURE_DW0_TYPE_DSIS 3
> +#define CDAT_STRUCTURE_DW0_TYPE_DSEMTS 4
> +#define CDAT_STRUCTURE_DW0_TYPE_SSLBIS 5
> +
> +#define CDAT_STRUCTURE_DW0_LENGTH 0xffff0000
> +
> +#define CXL_DOE_PROTOCOL_TABLE_ACCESS 2
> +
> +/**
> + * struct cxl_cdat - CXL CDAT data
> + *
> + * @table: cache of CDAT table
> + * @length: length of cached CDAT table
> + */
> +struct cxl_cdat {
> + void *table;
> + size_t length;
> +};
> +
> +#endif /* !__CXL_CDAT_H__ */
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 7672789c3225..dd5d1da412ca 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -4,10 +4,12 @@
> #include <linux/device.h>
> #include <linux/delay.h>
> #include <linux/pci.h>
> +#include <linux/pci-doe.h>
> #include <cxlpci.h>
> #include <cxlmem.h>
> #include <cxl.h>
> #include "core.h"
> +#include "cdat.h"
>
> /**
> * DOC: cxl core pci
> @@ -452,3 +454,170 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm)
> return 0;
> }
> EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);
> +
> +static struct pci_doe_mb *find_cdat_doe(struct device *uport)
> +{
> + struct cxl_memdev *cxlmd;
> + struct cxl_dev_state *cxlds;
> + unsigned long index;
> + void *entry;
> +
> + cxlmd = to_cxl_memdev(uport);
> + cxlds = cxlmd->cxlds;
> +
> + xa_for_each(&cxlds->doe_mbs, index, entry) {
> + struct pci_doe_mb *cur = entry;
> +
> + if (pci_doe_supports_prot(cur, PCI_DVSEC_VENDOR_ID_CXL,
> + CXL_DOE_PROTOCOL_TABLE_ACCESS))
> + return cur;
> + }
> +
> + return NULL;
> +}
> +
> +#define CDAT_DOE_REQ(entry_handle) \
> + (FIELD_PREP(CXL_DOE_TABLE_ACCESS_REQ_CODE, \
> + CXL_DOE_TABLE_ACCESS_REQ_CODE_READ) | \
> + FIELD_PREP(CXL_DOE_TABLE_ACCESS_TABLE_TYPE, \
> + CXL_DOE_TABLE_ACCESS_TABLE_TYPE_CDATA) | \
> + FIELD_PREP(CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE, (entry_handle)))
> +
> +static void cxl_doe_task_complete(struct pci_doe_task *task)
> +{
> + complete(task->private);
> +}
> +
> +#define CDAT_DOE_TASK(req, req_sz, rsp, rsp_sz, comp) \
I was hoping this could save some more typing by calculating sizes of
the buffers internally. I'll take a shot at that as I apply it.
> +{ \
> + .prot.vid = PCI_DVSEC_VENDOR_ID_CXL, \
> + .prot.type = CXL_DOE_PROTOCOL_TABLE_ACCESS, \
> + .request_pl = req, \
> + .request_pl_sz = req_sz, \
> + .response_pl = rsp, \
> + .response_pl_sz = rsp_sz, \
> + .complete = cxl_doe_task_complete, \
> + .private = comp, \
...and since this one is DOE specific the completion can be declared
internally to the macro as well. Acutally, the request and response
payloads are identical in all usages so this can make the call sites
even smaller.
> +}
> +
> +static int cxl_cdat_get_length(struct device *dev,
> + struct pci_doe_mb *cdat_doe,
> + size_t *length)
> +{
> + u32 cdat_request_pl = CDAT_DOE_REQ(0);
> + u32 cdat_response_pl[32];
> + DECLARE_COMPLETION_ONSTACK(c);
> + struct pci_doe_task task = CDAT_DOE_TASK(&cdat_request_pl,
> + sizeof(cdat_request_pl),
> + cdat_response_pl,
> + sizeof(cdat_response_pl),
> + &c);
> + int rc;
> +
> + rc = pci_doe_submit_task(cdat_doe, &task);
> + if (rc < 0) {
> + dev_err(dev, "DOE submit failed: %d", rc);
> + return rc;
> + }
> + wait_for_completion(&c);
> + if (task.rv < sizeof(u32))
> + return -EIO;
> +
> + *length = cdat_response_pl[1];
> + dev_dbg(dev, "CDAT length %zu\n", *length);
> +
> + return 0;
> +}
> +
> +static int cxl_cdat_read_table(struct device *dev,
> + struct pci_doe_mb *cdat_doe,
> + struct cxl_cdat *cdat)
> +{
> + size_t length = cdat->length;
> + u32 *data = cdat->table;
> + int entry_handle = 0;
> +
> + do {
> + u32 cdat_request_pl = CDAT_DOE_REQ(entry_handle);
> + u32 cdat_response_pl[32];
> + DECLARE_COMPLETION_ONSTACK(c);
> + struct pci_doe_task task = CDAT_DOE_TASK(&cdat_request_pl,
> + sizeof(cdat_request_pl),
> + cdat_response_pl,
> + sizeof(cdat_response_pl),
> + &c);
> + size_t entry_dw;
> + u32 *entry;
> + int rc;
> +
> + rc = pci_doe_submit_task(cdat_doe, &task);
> + if (rc < 0) {
> + dev_err(dev, "DOE submit failed: %d", rc);
> + return rc;
> + }
> + wait_for_completion(&c);
> + /* 1 DW header + 1 DW data min */
> + if (task.rv < (2 * sizeof(u32)))
> + return -EIO;
> +
> + /* Get the CXL table access header entry handle */
> + entry_handle = FIELD_GET(CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE,
> + cdat_response_pl[0]);
> + entry = cdat_response_pl + 1;
> + entry_dw = task.rv / sizeof(u32);
> + /* Skip Header */
> + entry_dw -= 1;
> + entry_dw = min(length / sizeof(u32), entry_dw);
> + /* Prevent length < 1 DW from causing a buffer overflow */
> + if (entry_dw) {
> + memcpy(data, entry, entry_dw * sizeof(u32));
> + length -= entry_dw * sizeof(u32);
> + data += entry_dw;
> + }
> + } while (entry_handle != CXL_DOE_TABLE_ACCESS_LAST_ENTRY);
> +
> + return 0;
> +}
> +
> +/**
> + * read_cdat_data - Read the CDAT data on this port
> + * @port: Port to read data from
> + *
> + * This call will sleep waiting for responses from the DOE mailbox.
> + */
> +void read_cdat_data(struct cxl_port *port)
> +{
> + static struct pci_doe_mb *cdat_doe;
Why is this variable static?
> + struct device *dev = &port->dev;
> + struct device *uport = port->uport;
> + size_t cdat_length;
> + int rc;
> +
> + cdat_doe = find_cdat_doe(uport);
> + if (!cdat_doe) {
> + dev_dbg(dev, "No CDAT mailbox\n");
> + return;
> + }
> +
> + port->cdat_available = true;
> +
> + if (cxl_cdat_get_length(dev, cdat_doe, &cdat_length)) {
> + dev_dbg(dev, "No CDAT length\n");
> + return;
> + }
> +
> + port->cdat.table = devm_kzalloc(dev, cdat_length, GFP_KERNEL);
> + if (!port->cdat.table)
> + return;
> +
> + port->cdat.length = cdat_length;
> + rc = cxl_cdat_read_table(dev, cdat_doe, &port->cdat);
> + if (rc) {
> + /* Don't leave table data allocated on error */
> + devm_kfree(dev, port->cdat.table);
> + port->cdat.table = NULL;
> + port->cdat.length = 0;
> + dev_err(dev, "CDAT data read error\n");
> + }
> +}
> +EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 570bd9f8141b..64ea8c80b917 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -8,6 +8,7 @@
> #include <linux/bitfield.h>
> #include <linux/bitops.h>
> #include <linux/io.h>
> +#include "cdat.h"
>
> /**
> * DOC: cxl objects
> @@ -289,6 +290,8 @@ struct cxl_nvdimm {
> * @component_reg_phys: component register capability base address (optional)
> * @dead: last ep has been removed, force port re-creation
> * @depth: How deep this port is relative to the root. depth 0 is the root.
> + * @cdat: Cached CDAT data
> + * @cdat_available: Should a CDAT attribute be available in sysfs
> */
> struct cxl_port {
> struct device dev;
> @@ -301,6 +304,8 @@ struct cxl_port {
> resource_size_t component_reg_phys;
> bool dead;
> unsigned int depth;
> + struct cxl_cdat cdat;
> + bool cdat_available;
> };
>
> /**
> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> index fce1c11729c2..eec597dbe763 100644
> --- a/drivers/cxl/cxlpci.h
> +++ b/drivers/cxl/cxlpci.h
> @@ -74,4 +74,5 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
> int devm_cxl_port_enumerate_dports(struct cxl_port *port);
> struct cxl_dev_state;
> int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm);
> +void read_cdat_data(struct cxl_port *port);
> #endif /* __CXL_PCI_H__ */
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 3cf308f114c4..08b8ac76f87b 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -53,6 +53,9 @@ static int cxl_port_probe(struct device *dev)
> struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport);
> struct cxl_dev_state *cxlds = cxlmd->cxlds;
>
> + /* Cache the data early to ensure is_visible() works */
> + read_cdat_data(port);
> +
> get_device(&cxlmd->dev);
> rc = devm_add_action_or_reset(dev, schedule_detach, cxlmd);
> if (rc)
> @@ -78,10 +81,61 @@ static int cxl_port_probe(struct device *dev)
> return 0;
> }
>
> +static ssize_t cdat_read(struct file *filp, struct kobject *kobj,
> + struct bin_attribute *bin_attr, char *buf,
> + loff_t offset, size_t count)
> +{
> + struct device *dev = kobj_to_dev(kobj);
> + struct cxl_port *port = to_cxl_port(dev);
> +
> + if (!port->cdat_available)
> + return -ENXIO;
> +
> + if (!port->cdat.table)
> + return 0;
> +
> + return memory_read_from_buffer(buf, count, &offset,
> + port->cdat.table,
> + port->cdat.length);
> +}
> +
> +static BIN_ATTR_ADMIN_RO(cdat, 0);
> +
> +static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj,
> + struct bin_attribute *attr, int i)
> +{
> + struct device *dev = kobj_to_dev(kobj);
> + struct cxl_port *port = to_cxl_port(dev);
> +
> + if ((attr == &bin_attr_cdat) && port->cdat_available)
> + return attr->attr.mode;
> +
> + return 0;
> +}
> +
> +static struct bin_attribute *cxl_cdat_bin_attributes[] = {
> + &bin_attr_cdat,
> + NULL,
> +};
> +
> +static struct attribute_group cxl_cdat_attribute_group = {
> + .name = "CDAT",
Why does it need its own directory? I'll just fix this up to drop the
extra CDAT directory, and rename the attribute file to CDAT directly.
> + .bin_attrs = cxl_cdat_bin_attributes,
> + .is_bin_visible = cxl_port_bin_attr_is_visible,
> +};
> +
> +static const struct attribute_group *cxl_port_attribute_groups[] = {
> + &cxl_cdat_attribute_group,
> + NULL,
> +};
> +
> static struct cxl_driver cxl_port_driver = {
> .name = "cxl_port",
> .probe = cxl_port_probe,
> .id = CXL_DEVICE_PORT,
> + .drv = {
> + .dev_groups = cxl_port_attribute_groups,
> + },
> };
>
> module_cxl_driver(cxl_port_driver);
> --
> 2.35.3
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH V14 6/7] cxl/port: Read CDAT table
2022-07-15 3:04 ` [PATCH V14 6/7] cxl/port: Read CDAT table ira.weiny
2022-07-16 3:27 ` Dan Williams
@ 2022-07-19 1:19 ` Dan Williams
1 sibling, 0 replies; 20+ messages in thread
From: Dan Williams @ 2022-07-19 1:19 UTC (permalink / raw)
To: ira.weiny, Dan Williams, Bjorn Helgaas, Jonathan Cameron
Cc: Ira Weiny, Lukas Wunner, Alison Schofield, Vishal Verma,
Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl, linux-pci
ira.weiny@ wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> The OS will need CDAT data from CXL devices to properly set up
> interleave sets. Currently this is supported through a DOE mailbox
> which supports CDAT.
>
> Search the DOE mailboxes available, query CDAT data, and cache the data
> for later parsing.
>
> Provide a sysfs binary attribute to allow dumping of the CDAT.
>
> Binary dumping is modeled on /sys/firmware/ACPI/tables/
>
> The ability to dump this table will be very useful for emulation of real
> devices once they become available as QEMU CXL type 3 device emulation will
> be able to load this file in.
>
> This does not support table updates at runtime. It will always provide
> whatever was there when first cached. Handling of table updates can be
> implemented later.
>
> Finally create a complete list of CDAT defines within cdat.h for code
> wishing to decode the CDAT table.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
>
> ---
> Changes from V13:
> Dan:
> Add entry in Documentation/ABI/testing/sysfs-bus-cxl
> Remove table parsing defines.
> s/cdat_sup/cdat_available
> s/cdat_mb/cdat_doe/
> Don't check endpoint in find_cdat_doe()
> Create CDAT_DOE_TASK macro
>
> Changes from V12:
> Fix checking for task.rv for errors
> Ensure no over run of non-DW aligned buffer length's
>
> Changes from V11:
> Adjust for the use of DOE mailbox xarray
> Dan Williams:
> Remove unnecessary get/put device
> Use new BIN_ATTR_ADMIN_RO macro
> Flag that CDAT was supported
> If there is a read error then the CDAT sysfs
> will return a 0 length entry
>
> Changes from V10:
> Ben Widawsky
> Failure to find CDAT should be a debug message not error
> Remove reference to cdat_mb from the port object
> Dropped [PATCH V10 5/9] cxl/port: Find a DOE mailbox which supports
> CDAT
> Iterate the mailboxes for the CDAT one each time.
> Define CXL_DOE_TABLE_ACCESS_LAST_ENTRY and add comment about
> it's use.
>
> Changes from V9:
> Add debugging output
> Jonathan Cameron
> Move read_cdat to port probe by using dev_groups for the
> sysfs attributes. This avoids issues with using devm
> before the driver is loaded while making sure the CDAT
> binary is available.
>
> Changes from V8:
> Fix length print format
> Incorporate feedback from Jonathan
> Move all this to cxl_port which can help support switches when
> the time comes.
>
> Changes from V6:
> Fix issue with devm use
> Move cached cdat data to cxl_dev_state
> Use new pci_doe_submit_task()
> Ensure the aux driver is locked while processing tasks
> Rebased on cxl-pending
>
> Changes from V5:
> Add proper guards around cdat.h
> Split out finding the CDAT DOE mailbox
> Use cxl_cdat to group CDAT data together
> Adjust to use auxiliary_find_device() to find the DOE device
> which supplies the CDAT protocol.
> Rebased to latest
> Remove dev_dbg(length)
> Remove unneeded DOE Table access defines
> Move CXL_DOE_PROTOCOL_TABLE_ACCESS define into this patch where
> it is used
>
> Changes from V4:
> Split this into it's own patch
> Rearchitect this such that the memdev driver calls into the DOE
> driver via the cxl_mem state object. This allows CDAT data to
> come from any type of cxl_mem object not just PCI DOE.
> Rebase on new struct cxl_dev_state
> ---
> Documentation/ABI/testing/sysfs-bus-cxl | 10 ++
> drivers/cxl/cdat.h | 61 +++++++++
> drivers/cxl/core/pci.c | 169 ++++++++++++++++++++++++
> drivers/cxl/cxl.h | 5 +
> drivers/cxl/cxlpci.h | 1 +
> drivers/cxl/port.c | 54 ++++++++
> 6 files changed, 300 insertions(+)
> create mode 100644 drivers/cxl/cdat.h
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
> index 1fd5984b6158..6fb6459466f8 100644
> --- a/Documentation/ABI/testing/sysfs-bus-cxl
> +++ b/Documentation/ABI/testing/sysfs-bus-cxl
> @@ -164,3 +164,13 @@ Description:
> expander memory (type-3). The 'target_type' attribute indicates
> the current setting which may dynamically change based on what
> memory regions are activated in this decode hierarchy.
> +
> +What: /sys/bus/cxl/devices/endpointX/CDAT/cdat
> +Date: July, 2022
> +KernelVersion: v5.19
> +Contact: linux-cxl@vger.kernel.org
> +Description:
> + (RO) If this sysfs entry is not present no DOE mailbox was
> + found to support CDAT data. If it is present and the length of
> + the data is 0 reading the CDAT data failed. Otherwise the CDAT
> + data is reported.
> diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h
> new file mode 100644
> index 000000000000..67010717ffca
> --- /dev/null
> +++ b/drivers/cxl/cdat.h
> @@ -0,0 +1,61 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __CXL_CDAT_H__
> +#define __CXL_CDAT_H__
> +
> +/*
> + * Coherent Device Attribute table (CDAT)
> + *
> + * Specification available from UEFI.org
> + *
> + * Whilst CDAT is defined as a single table, the access via DOE maiboxes is
> + * done one entry at a time, where the first entry is the header.
> + */
> +
> +#define CXL_DOE_TABLE_ACCESS_REQ_CODE 0x000000ff
> +#define CXL_DOE_TABLE_ACCESS_REQ_CODE_READ 0
> +#define CXL_DOE_TABLE_ACCESS_TABLE_TYPE 0x0000ff00
> +#define CXL_DOE_TABLE_ACCESS_TABLE_TYPE_CDATA 0
> +#define CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE 0xffff0000
> +#define CXL_DOE_TABLE_ACCESS_LAST_ENTRY 0xffff
> +
> +/*
> + * CDAT entries are little endian and are read from PCI config space which
> + * is also little endian.
> + * As such, on a big endian system these will have been reversed.
> + * This prevents us from making easy use of packed structures.
> + * Style form pci_regs.h
> + */
I do not get this... the PCI ops on big endian machines are already
handling the fact that PCI config space is in le-order. So you should be
able to use data structure definitions directly just like any other PCI
config data payload.
I dropped this along with the other revisions I spotted for this patch.
> +
> +#define CDAT_HEADER_LENGTH_DW 4
> +#define CDAT_HEADER_LENGTH_BYTES (CDAT_HEADER_LENGTH_DW * sizeof(u32))
> +#define CDAT_HEADER_DW0_LENGTH 0xffffffff
> +#define CDAT_HEADER_DW1_REVISION 0x000000ff
> +#define CDAT_HEADER_DW1_CHECKSUM 0x0000ff00
> +/* CDAT_HEADER_DW2_RESERVED */
> +#define CDAT_HEADER_DW3_SEQUENCE 0xffffffff
> +
> +/* All structures have a common first DW */
> +#define CDAT_STRUCTURE_DW0_TYPE 0x000000ff
> +#define CDAT_STRUCTURE_DW0_TYPE_DSMAS 0
> +#define CDAT_STRUCTURE_DW0_TYPE_DSLBIS 1
> +#define CDAT_STRUCTURE_DW0_TYPE_DSMSCIS 2
> +#define CDAT_STRUCTURE_DW0_TYPE_DSIS 3
> +#define CDAT_STRUCTURE_DW0_TYPE_DSEMTS 4
> +#define CDAT_STRUCTURE_DW0_TYPE_SSLBIS 5
> +
> +#define CDAT_STRUCTURE_DW0_LENGTH 0xffff0000
Dropped these too since they are unused.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH V14 0/7] CXL: Read CDAT
2022-07-15 3:04 [PATCH V14 0/7] CXL: Read CDAT ira.weiny
` (6 preceding siblings ...)
2022-07-15 3:04 ` [PATCH V14 7/7] cxl/port: Introduce cxl_cdat_valid() ira.weiny
@ 2022-07-19 15:21 ` Jonathan Cameron
2022-07-19 19:23 ` Dan Williams
7 siblings, 1 reply; 20+ messages in thread
From: Jonathan Cameron @ 2022-07-19 15:21 UTC (permalink / raw)
To: ira.weiny
Cc: Dan Williams, Bjorn Helgaas, Lukas Wunner, Alison Schofield,
Vishal Verma, Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl,
linux-pci
On Thu, 14 Jul 2022 20:04:17 -0700
ira.weiny@intel.com wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> Details of changes are in the individual patches.
>
> Major changes from V13:[10]
> Dan minor updates
> Willy's suggestion of documentation is good but I'm deferring it until
> we get the location of the PCI mailboxes settled.
> Drop retry CDAT patch
> Drop DSMAS patch
> Rebased on latest cxl-pending
>
> CXL drivers need various data which are provided through generic DOE mailboxes
> as defined in the PCIe 6.0 spec.[1]
>
> One such data is the Coherent Device Attribute Table (CDAT). CDAT data provides
> coherent information about the various devices in the system. It was developed
> because systems no longer have a priori knowledge of all coherent devices
> within a system. CDAT describes the coherent characteristics of the
> components on the CXL bus separate from system configurations. The OS can
> then, for example, use this information to form correct interleave sets.
>
> To begin reading the CDAT the OS must have support to access the DOE mailboxes
> provided by the CXL devices.
>
> Because DOE is not specific to DOE but is provided within the PCI spec, the
> series adds PCI DOE capability library functions. These functions allow for
> the iteration of the DOE capabilities on a device as well as creating
> pci_doe_mb structures which can control the operation of the DOE state machine.
>
> For now the iteration of and storage of the DOE mailboxes is done on memdev
> objects within the CXL stack. When this is needed in more generic code this
> can be lifted later.
>
> This work was tested using qemu.
>
> [0] https://lore.kernel.org/linux-cxl/20211105235056.3711389-1-ira.weiny@intel.com/
> [1] https://pcisig.com/specifications
> [2] https://lore.kernel.org/qemu-devel/20210202005948.241655-1-ben.widawsky@intel.com/
> [3] https://lore.kernel.org/linux-cxl/20220201071952.900068-1-ira.weiny@intel.com/
> [4] https://lore.kernel.org/linux-cxl/20220330235920.2800929-1-ira.weiny@intel.com/
> [5] https://lore.kernel.org/linux-cxl/20220414203237.2198665-1-ira.weiny@intel.com/
> [6] https://lore.kernel.org/linux-cxl/20220531152632.1397976-1-ira.weiny@intel.com/
> [7] https://lore.kernel.org/linux-cxl/20220605005049.2155874-1-ira.weiny@intel.com/
> [8] https://lore.kernel.org/linux-cxl/20220610202259.3544623-1-ira.weiny@intel.com/
> [9] https://lore.kernel.org/linux-cxl/20220628041527.742333-1-ira.weiny@intel.com/
> [10] https://lore.kernel.org/linux-cxl/20220705154932.2141021-1-ira.weiny@intel.com/
>
>
> Previous changes
> ================
>
> Changes from V12:[9]
> A couple of bug fixes in the new XArray stuff
> Remove the IRQ support because I did not realize how that worked and it
> was complicating things.
> Remove busy retries and replace with an error as there is no good way
> to ensure it will work.
This is fine for userspace access, but I think we probably will want retries
once we are using it in kernel. Whilst we'd not expect it to be common as
per (very late) reply I sent to v13 discussion, the CDAT table can change
all on it's own (as far as software can see). I'd expect it to be a once in
a blue moon thing though.
> Other code clean ups mentioned in the individual patches.
>
> Changes from V11:[8]
> The major change in this version is to remove the workqueue from the
> internal implementation of the state machine. A single ordered
> workqueue within each mailbox processes tasks submitted. This
> workqueue takes care of all locking and guarantees that tasks are
> completed in the order submitted. Any synchronization which is
> required between tasks will need to be handled by the user of the
> mailbox. However, the user can depend on work items being completed in
> the order they are submitted. So a single thread submitter is
> guaranteed to get all work items completed in order. This also aids in
> the support of a single mailbox supporting multiple protocols. Each
> protocol could have a separate thread submitting tasks for that
> protocol. The mailbox object will ensure that each protocol task is
> complete before another task starts. But multiple user threads can be
> submitting tasks for different protocols all at the same time without
> regard to other protocols being used.
>
> XArrays are used throughout the series.
>
> Other minor changes are noted in the individual patches.
>
> Changes from V10:[7]
> Address Ben Widawsky's comments
> Protect against potentially malicious devices.
> Fix ownership issue of cdat_mb
>
> Changes from V9:[6]
> Address feedback from
> Lukas Wunner, Davidlohr Bueso, Jonathan Cameron,
> Alison Schofield, and Ben Widawsky
> Details in each individual patch.
>
> Changes from V8:[5]
> For this version I've punted a bit to get it out and drop the auxiliary
> bus functionality. I like where Jonathan is going with the port driver
> idea. I think eventually the irq/mailbox creation will need to be more
> generic in a PCI port driver. I've modeled this version on such an
> architecture but used the CXL port for the time being.
>
> From Dan
> Drop the auxiliary bus/device
> From Jonathan
> Cleanups
> From Bjorn
> Clean up commit messages
> move pci-doe.c to doe.c
> Clean up PCI spec references
> Ensure all messages use pci_*()
> Add offset to error messages to distinguish mailboxes
> use hex for DOE offsets
> Print 4 nibbles for Vendor ID and 2 for type.
> s/irq/IRQ in comments
> Fix long lines
> Fix typos
>
>
> Changes from V7:[4]
> Avoid code bloat by making pci-doe.c conditional on CONFIG_PCI_DOE
> which is auto selected by the CXL_PCI config option.
> Minor code clean ups
> Fix bug in pci_doe_supports_prot()
> Rebase to cxl-pending
>
> Changes from V6:[3]
> The big change is the removal of the auxiliary bus code from the PCI
> layer. The auxiliary bus usage is now in the CXL layer. The PCI layer
> provides helpers for subsystems to utilize DOE mailboxes by creating a
> pci_doe_mb object which controls a state machine for that mailbox
> capability. The CXL layer wraps this object in an auxiliary device and
> driver which can then be used to determine if the kernel is controlling
> the capability or it is available to be used by user space. Reads from
> user space via lspci are allowed. Writes are allowed but flagged via a
> tainting the kernel.
>
> Feedback from Bjorn, Jonathan, and Dan
> Details in each patch
>
> Changes from V5:[0]
>
> Rework the patch set to split PCI vs CXL changes
> Also make each change a bit more stand alone for easier review
> Add cxl_cdat structure
> Put CDAT related data structures in cdat.h
> Clarify some device lifetimes with comments
> Incorporate feedback from Jonathan, Bjorn and Dan
> The bigest change is placing the DOE scanning code into the
> pci_doe driver (part of the PCI codre).
> Validate the CDAT when it is read rather than before DSMAS
> parsing
> Do not report DSMAS failure as an error, report a warning and
> keep going.
> Retry reading the table 1 time.
> Update commit messages and this cover letter
>
>
>
> Ira Weiny (5):
> PCI: Replace magic constant for PCI Sig Vendor ID
> cxl/pci: Create PCI DOE mailbox's for memory devices
> driver-core: Introduce BIN_ATTR_ADMIN_{RO,RW}
> cxl/port: Read CDAT table
> cxl/port: Introduce cxl_cdat_valid()
>
> Jonathan Cameron (2):
> PCI: Add vendor ID for the PCI SIG
> PCI/DOE: Add DOE mailbox support functions
>
> .clang-format | 1 +
> Documentation/ABI/testing/sysfs-bus-cxl | 10 +
> drivers/cxl/Kconfig | 1 +
> drivers/cxl/cdat.h | 63 +++
> drivers/cxl/core/pci.c | 206 +++++++++
> drivers/cxl/cxl.h | 5 +
> drivers/cxl/cxlmem.h | 3 +
> drivers/cxl/cxlpci.h | 1 +
> drivers/cxl/pci.c | 44 ++
> drivers/cxl/port.c | 54 +++
> drivers/pci/Kconfig | 3 +
> drivers/pci/Makefile | 1 +
> drivers/pci/doe.c | 546 ++++++++++++++++++++++++
> drivers/pci/probe.c | 2 +-
> include/linux/pci-doe.h | 79 ++++
> include/linux/pci_ids.h | 1 +
> include/linux/sysfs.h | 16 +
> include/uapi/linux/pci_regs.h | 29 +-
> 18 files changed, 1063 insertions(+), 2 deletions(-)
> create mode 100644 drivers/cxl/cdat.h
> create mode 100644 drivers/pci/doe.c
> create mode 100644 include/linux/pci-doe.h
>
>
> base-commit: b060edfd8cdd52bc8648392500bf152a8dd6d4c5
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH V14 3/7] PCI/DOE: Add DOE mailbox support functions
2022-07-15 3:04 ` [PATCH V14 3/7] PCI/DOE: Add DOE mailbox support functions ira.weiny
@ 2022-07-19 16:35 ` Jonathan Cameron
2022-07-19 19:16 ` Ira Weiny
0 siblings, 1 reply; 20+ messages in thread
From: Jonathan Cameron @ 2022-07-19 16:35 UTC (permalink / raw)
To: ira.weiny
Cc: Dan Williams, Bjorn Helgaas, Li, Ming, Bjorn Helgaas,
Matthew Wilcox, Lukas Wunner, Alison Schofield, Vishal Verma,
Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl, linux-pci
On Thu, 14 Jul 2022 20:04:20 -0700
ira.weiny@intel.com wrote:
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> Introduced in a PCIe r6.0, sec 6.30, DOE provides a config space based
> mailbox with standard protocol discovery. Each mailbox is accessed
> through a DOE Extended Capability.
>
> Each DOE mailbox must support the DOE discovery protocol in addition to
> any number of additional protocols.
>
> Define core PCIe functionality to manage a single PCIe DOE mailbox at a
> defined config space offset. Functionality includes iterating,
> creating, query of supported protocol, and task submission. Destruction
> of the mailboxes is device managed.
>
> Cc: "Li, Ming" <ming4.li@intel.com>
> Cc: Bjorn Helgaas <helgaas@kernel.org>
> Cc: Matthew Wilcox <willy@infradead.org>
> Acked-by: Bjorn Helgaas <helgaas@kernel.org>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Co-developed-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Hi Ira,
Thanks for persisting with this!
So, I think this works, but there is at least one 'sleep' I can't
see a purpose for. I think it's just a left over from refactoring.
A few other more trivial things inline.
Thanks,
Jonathan
>
>> # Endpoint library must be initialized before its users
> obj-$(CONFIG_PCI_ENDPOINT) += endpoint/
> diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c
> new file mode 100644
> index 000000000000..12c3762be22f
> --- /dev/null
> +++ b/drivers/pci/doe.c
> @@ -0,0 +1,546 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Data Object Exchange
> + * PCIe r6.0, sec 6.30 DOE
> + *
> + * Copyright (C) 2021 Huawei
> + * Jonathan Cameron <Jonathan.Cameron@huawei.com>
> + *
> + * Copyright (C) 2022 Intel Corporation
> + * Ira Weiny <ira.weiny@intel.com>
> + */
> +
> +#define dev_fmt(fmt) "DOE: " fmt
> +
> +#include <linux/bitfield.h>
> +#include <linux/delay.h>
> +#include <linux/jiffies.h>
> +#include <linux/mutex.h>
> +#include <linux/pci.h>
> +#include <linux/pci-doe.h>
> +#include <linux/workqueue.h>
> +
> +#define PCI_DOE_PROTOCOL_DISCOVERY 0
> +
> +#define PCI_DOE_BUSY_MAX_RETRIES 16
Left over from removed code.
> +static int pci_doe_wait(struct pci_doe_mb *doe_mb, unsigned long timeout)
This feels misnamed to me now. It's not waiting for the DOE, it's
just sleeping unless we cancel. The actual poll / wait is handled
outside this. pci_doe_sleep_unless_cancel() maybe?
> +{
> + if (wait_event_timeout(doe_mb->wq,
> + test_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags),
> + timeout))
> + return -EIO;
> + return 0;
> +}
> +static int pci_doe_send_req(struct pci_doe_mb *doe_mb,
> + struct pci_doe_task *task)
> +{
> + struct pci_dev *pdev = doe_mb->pdev;
> + int offset = doe_mb->cap_offset;
> + u32 val;
> + int i;
> +
> + /*
> + * Check the DOE busy bit is not set. If it is set, this could indicate
> + * someone other than Linux (e.g. firmware) is using the mailbox. Note
> + * it is expected that firmware and OS will negotiate access rights via
> + * an, as yet to be defined method.
trivial: an, as yet to be defined, method.
> + */
> + pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
> + if (FIELD_GET(PCI_DOE_STATUS_BUSY, val))
> + return -EBUSY;
> +
> + if (FIELD_GET(PCI_DOE_STATUS_ERROR, val))
> + return -EIO;
> +
> + /* Write DOE Header */
> + val = FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_VID, task->prot.vid) |
> + FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, task->prot.type);
> + pci_write_config_dword(pdev, offset + PCI_DOE_WRITE, val);
> + /* Length is 2 DW of header + length of payload in DW */
> + pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
> + FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH,
> + 2 + task->request_pl_sz /
> + sizeof(u32)));
> + for (i = 0; i < task->request_pl_sz / sizeof(u32); i++)
> + pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
> + task->request_pl[i]);
> +
> + pci_doe_write_ctrl(doe_mb, PCI_DOE_CTRL_GO);
> +
> + /* Request is sent - now wait for poll or IRQ */
Could drop the IRQ given not currently handling. Though I suppose it's correct
documentation for this function, so can leave it if preferred.
More than possible we'll get a follow up patch dropping it though from
someone doing cleanup.
> + return 0;
> +}
> +
...
> +
> +static void doe_statemachine_work(struct work_struct *work)
> +{
> + struct pci_doe_task *task = container_of(work, struct pci_doe_task,
> + work);
> + struct pci_doe_mb *doe_mb = task->doe_mb;
> + struct pci_dev *pdev = doe_mb->pdev;
> + int offset = doe_mb->cap_offset;
> + unsigned long timeout_jiffies;
> + u32 val;
> + int rc;
> +
> + if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags)) {
> + signal_task_complete(task, -EIO);
> + return;
> + }
> +
> + /* Send request */
> + rc = pci_doe_send_req(doe_mb, task);
> +
nitpick, but blank line separating call from error handling reduces
readability in my opinion.
> + if (rc) {
> + /*
> + * The specification does not provide any guidance on how to
> + * resolve conflicting requests from other entities.
> + * Furthermore, it is likely that busy will not be detected
> + * most of the time. Flag any detection of status busy with an
> + * error.
> + */
> + if (rc == -EBUSY)
> + dev_err_ratelimited(&pdev->dev, "[%x] busy detected; another entity is sending conflicting requests\n",
> + offset);
> + signal_task_abort(task, rc);
> + return;
> + }
> +
> + timeout_jiffies = jiffies + PCI_DOE_TIMEOUT;
> + rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL);
What's this particular wait for? I think you can just move directly to checking
if the response is ready.
> + if (rc) {
> + signal_task_abort(task, rc);
> + return;
> + }
> +
> + /* Poll for response */
> +retry_resp:
> + pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
> + if (FIELD_GET(PCI_DOE_STATUS_ERROR, val)) {
> + signal_task_abort(task, -EIO);
> + return;
> + }
> +
> + if (!FIELD_GET(PCI_DOE_STATUS_DATA_OBJECT_READY, val)) {
> + if (time_after(jiffies, timeout_jiffies)) {
> + signal_task_abort(task, -EIO);
> + return;
> + }
> + rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL);
> + if (rc) {
> + signal_task_abort(task, rc);
> + return;
> + }
> + goto retry_resp;
> + }
> +
> + rc = pci_doe_recv_resp(doe_mb, task);
> + if (rc < 0) {
> + signal_task_abort(task, rc);
> + return;
> + }
> +
> + signal_task_complete(task, rc);
> +}
> +
> +/**
> + * pci_doe_supports_prot() - Return if the DOE instance supports the given
> + * protocol
> + * @doe_mb: DOE mailbox capability to query
> + * @vid: Protocol Vendor ID
> + * @type: Protocol type
> + *
> + * RETURNS: True if the DOE mailbox supports the protocol specified
> + */
> +bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type)
> +{
> + unsigned long index;
> + void *entry;
> +
> + /* The discovery protocol must always be supported */
> + if (vid == PCI_VENDOR_ID_PCI_SIG && type == PCI_DOE_PROTOCOL_DISCOVERY)
> + return true;
Given how cheap this look up is now it's all in xarray, we could drop this
'optimization'. I'm fairly sure the discovery protocol will always be
discovered (spec says it must be returned when calling itself as the fist
protocol).
> +
> + xa_for_each(&doe_mb->prots, index, entry)
> + if (entry == pci_doe_xa_prot_entry(vid, type))
> + return true;
> +
> + return false;
> +}
> +EXPORT_SYMBOL_GPL(pci_doe_supports_prot);
> +EXPORT_SYMBOL_GPL(pci_doe_submit_task);
> diff --git a/include/linux/pci-doe.h b/include/linux/pci-doe.h
> new file mode 100644
> index 000000000000..c77f6258c996
> --- /dev/null
> +++ b/include/linux/pci-doe.h
> @@ -0,0 +1,79 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Data Object Exchange
> + * PCIe r6.0, sec 6.30 DOE
> + *
> + * Copyright (C) 2021 Huawei
> + * Jonathan Cameron <Jonathan.Cameron@huawei.com>
> + *
> + * Copyright (C) 2022 Intel Corporation
> + * Ira Weiny <ira.weiny@intel.com>
> + */
> +
> +#ifndef LINUX_PCI_DOE_H
> +#define LINUX_PCI_DOE_H
> +
> +#include <linux/completion.h>
include not needed any more.
Thanks,
Jonathan
> +
> +struct pci_doe_protocol {
> + u16 vid;
> + u8 type;
> +};
> +
> +struct pci_doe_mb;
> +
> +/**
> + * struct pci_doe_task - represents a single query/response
> + *
> + * @prot: DOE Protocol
> + * @request_pl: The request payload
> + * @request_pl_sz: Size of the request payload (bytes)
> + * @response_pl: The response payload
> + * @response_pl_sz: Size of the response payload (bytes)
> + * @rv: Return value. Length of received response or error (bytes)
> + * @complete: Called when task is complete
> + * @private: Private data for the consumer
> + * @work: Used internally by the mailbox
> + * @doe_mb: Used internally by the mailbox
> + *
> + * The payload sizes and rv are specified in bytes with the following
> + * restrictions concerning the protocol.
> + *
> + * 1) The request_pl_sz must be a multiple of double words (4 bytes)
> + * 2) The response_pl_sz must be >= a single double word (4 bytes)
> + * 3) rv is returned as bytes but it will be a multiple of double words
> + *
> + * NOTE there is no need for the caller to initialize work or doe_mb.
> + */
> +struct pci_doe_task {
> + struct pci_doe_protocol prot;
> + u32 *request_pl;
> + size_t request_pl_sz;
> + u32 *response_pl;
> + size_t response_pl_sz;
> + int rv;
> + void (*complete)(struct pci_doe_task *task);
> + void *private;
> +
> + /* No need for the user to initialize these fields */
> + struct work_struct work;
> + struct pci_doe_mb *doe_mb;
> +};
> +
> +/**
> + * pci_doe_for_each_off - Iterate each DOE capability
> + * @pdev: struct pci_dev to iterate
> + * @off: u16 of config space offset of each mailbox capability found
> + */
> +#define pci_doe_for_each_off(pdev, off) \
> + for (off = pci_find_next_ext_capability(pdev, off, \
> + PCI_EXT_CAP_ID_DOE); \
> + off > 0; \
> + off = pci_find_next_ext_capability(pdev, off, \
> + PCI_EXT_CAP_ID_DOE))
> +
> +struct pci_doe_mb *pcim_doe_create_mb(struct pci_dev *pdev, u16 cap_offset);
> +bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type);
> +int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task);
> +
> +#endif
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH V14 4/7] cxl/pci: Create PCI DOE mailbox's for memory devices
2022-07-15 3:04 ` [PATCH V14 4/7] cxl/pci: Create PCI DOE mailbox's for memory devices ira.weiny
@ 2022-07-19 16:38 ` Jonathan Cameron
0 siblings, 0 replies; 20+ messages in thread
From: Jonathan Cameron @ 2022-07-19 16:38 UTC (permalink / raw)
To: ira.weiny
Cc: Dan Williams, Bjorn Helgaas, Davidlohr Bueso, Lukas Wunner,
Alison Schofield, Vishal Verma, Dave Jiang, Ben Widawsky,
linux-kernel, linux-cxl, linux-pci
On Thu, 14 Jul 2022 20:04:21 -0700
ira.weiny@intel.com wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> DOE mailbox objects will be needed for various mailbox communications
> with each memory device.
>
> Iterate each DOE mailbox capability and create PCI DOE mailbox objects
> as found.
>
> It is not anticipated that this is the final resting place for the
> iteration of the DOE devices. The support of switch ports will drive
> this code into the PCIe side. In this imagined architecture the CXL
> port driver would then query into the PCI device for the DOE mailbox
> array.
>
> For now creating the mailboxes in the CXL port is good enough for the
> endpoints. Later PCIe ports will need to support this to support switch
> ports more generically.
>
> Cc: Dan Williams <dan.j.williams@intel.com>
> Cc: Davidlohr Bueso <dave@stgolabs.net>
> Cc: Lukas Wunner <lukas@wunner.de>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
LGTM
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH V14 5/7] driver-core: Introduce BIN_ATTR_ADMIN_{RO,RW}
2022-07-15 3:04 ` [PATCH V14 5/7] driver-core: Introduce BIN_ATTR_ADMIN_{RO,RW} ira.weiny
@ 2022-07-19 16:39 ` Jonathan Cameron
0 siblings, 0 replies; 20+ messages in thread
From: Jonathan Cameron @ 2022-07-19 16:39 UTC (permalink / raw)
To: ira.weiny
Cc: Dan Williams, Bjorn Helgaas, Krzysztof Wilczyński,
Greg Kroah-Hartman, Lukas Wunner, Alison Schofield, Vishal Verma,
Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl, linux-pci
On Thu, 14 Jul 2022 20:04:22 -0700
ira.weiny@intel.com wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> Many binary attributes need to limit access to CAP_SYS_ADMIN only; ie
> many binary attributes specify is_visible with 0400 or 0600.
>
> Make setting the permissions of such attributes more explicit by
> defining BIN_ATTR_ADMIN_{RO,RW}.
>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> Suggested-by: Krzysztof Wilczyński <kw@linux.com>
> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Seems sensible.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ---
> Changes from V12:
> Pick up review tag
> Bjorn:
> NOTE: this has a lot of similarities to
> https://lore.kernel.org/all/20210416205856.3234481-7-kw@linux.com/
> I'm not sure why that patch was not picked up. But I've
> added Krzysztof as a suggested by if that is ok?
>
> Changes from V11:
> New Patch
> ---
> include/linux/sysfs.h | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/include/linux/sysfs.h b/include/linux/sysfs.h
> index e3f1e8ac1f85..fd3fe5c8c17f 100644
> --- a/include/linux/sysfs.h
> +++ b/include/linux/sysfs.h
> @@ -235,6 +235,22 @@ struct bin_attribute bin_attr_##_name = __BIN_ATTR_WO(_name, _size)
> #define BIN_ATTR_RW(_name, _size) \
> struct bin_attribute bin_attr_##_name = __BIN_ATTR_RW(_name, _size)
>
> +
> +#define __BIN_ATTR_ADMIN_RO(_name, _size) { \
> + .attr = { .name = __stringify(_name), .mode = 0400 }, \
> + .read = _name##_read, \
> + .size = _size, \
> +}
> +
> +#define __BIN_ATTR_ADMIN_RW(_name, _size) \
> + __BIN_ATTR(_name, 0600, _name##_read, _name##_write, _size)
> +
> +#define BIN_ATTR_ADMIN_RO(_name, _size) \
> +struct bin_attribute bin_attr_##_name = __BIN_ATTR_ADMIN_RO(_name, _size)
> +
> +#define BIN_ATTR_ADMIN_RW(_name, _size) \
> +struct bin_attribute bin_attr_##_name = __BIN_ATTR_ADMIN_RW(_name, _size)
> +
> struct sysfs_ops {
> ssize_t (*show)(struct kobject *, struct attribute *, char *);
> ssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t);
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH V14 7/7] cxl/port: Introduce cxl_cdat_valid()
2022-07-16 2:26 ` Dan Williams
@ 2022-07-19 16:47 ` Jonathan Cameron
0 siblings, 0 replies; 20+ messages in thread
From: Jonathan Cameron @ 2022-07-19 16:47 UTC (permalink / raw)
To: Dan Williams
Cc: ira.weiny, Bjorn Helgaas, Lukas Wunner, Alison Schofield,
Vishal Verma, Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl,
linux-pci
On Fri, 15 Jul 2022 19:26:01 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> ira.weiny@ wrote:
> > From: Ira Weiny <ira.weiny@intel.com>
> >
> > The CDAT data is protected by a checksum and should be the proper
> > length.
> >
> > Introduce cxl_cdat_valid() to validate the data. While at it check and
> > store the sequence number.
>
> I am going to drop this one. Userspace can determine validity when it
> parses it. When the kernel grows a CDAT parser it will rely on the
> standard validation of ACPI-table-like structures from a future
> __acpi_table_parse_entries() derivative for this purpose.
OK, for now I guess.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH V14 3/7] PCI/DOE: Add DOE mailbox support functions
2022-07-19 16:35 ` Jonathan Cameron
@ 2022-07-19 19:16 ` Ira Weiny
2022-07-19 19:50 ` Ira Weiny
2022-07-20 11:24 ` Jonathan Cameron
0 siblings, 2 replies; 20+ messages in thread
From: Ira Weiny @ 2022-07-19 19:16 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Dan Williams, Bjorn Helgaas, Li, Ming, Bjorn Helgaas,
Matthew Wilcox, Lukas Wunner, Alison Schofield, Vishal Verma,
Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl, linux-pci
On Tue, Jul 19, 2022 at 05:35:53PM +0100, Jonathan Cameron wrote:
> On Thu, 14 Jul 2022 20:04:20 -0700
> ira.weiny@intel.com wrote:
>
> > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> >
> > Introduced in a PCIe r6.0, sec 6.30, DOE provides a config space based
> > mailbox with standard protocol discovery. Each mailbox is accessed
> > through a DOE Extended Capability.
> >
> > Each DOE mailbox must support the DOE discovery protocol in addition to
> > any number of additional protocols.
> >
> > Define core PCIe functionality to manage a single PCIe DOE mailbox at a
> > defined config space offset. Functionality includes iterating,
> > creating, query of supported protocol, and task submission. Destruction
> > of the mailboxes is device managed.
> >
> > Cc: "Li, Ming" <ming4.li@intel.com>
> > Cc: Bjorn Helgaas <helgaas@kernel.org>
> > Cc: Matthew Wilcox <willy@infradead.org>
> > Acked-by: Bjorn Helgaas <helgaas@kernel.org>
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > Co-developed-by: Ira Weiny <ira.weiny@intel.com>
> > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> Hi Ira,
>
> Thanks for persisting with this!
>
> So, I think this works, but there is at least one 'sleep' I can't
> see a purpose for. I think it's just a left over from refactoring.
>
> A few other more trivial things inline.
>
> Thanks,
>
> Jonathan
>
>
> >
> >> # Endpoint library must be initialized before its users
> > obj-$(CONFIG_PCI_ENDPOINT) += endpoint/
> > diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c
> > new file mode 100644
> > index 000000000000..12c3762be22f
> > --- /dev/null
> > +++ b/drivers/pci/doe.c
> > @@ -0,0 +1,546 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Data Object Exchange
> > + * PCIe r6.0, sec 6.30 DOE
> > + *
> > + * Copyright (C) 2021 Huawei
> > + * Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > + *
> > + * Copyright (C) 2022 Intel Corporation
> > + * Ira Weiny <ira.weiny@intel.com>
> > + */
> > +
> > +#define dev_fmt(fmt) "DOE: " fmt
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/delay.h>
> > +#include <linux/jiffies.h>
> > +#include <linux/mutex.h>
> > +#include <linux/pci.h>
> > +#include <linux/pci-doe.h>
> > +#include <linux/workqueue.h>
> > +
> > +#define PCI_DOE_PROTOCOL_DISCOVERY 0
> > +
> > +#define PCI_DOE_BUSY_MAX_RETRIES 16
> Left over from removed code.
I think Dan may have taken these. If so I'll send a clean up. If not I can
spin. Let me check.
>
> > +static int pci_doe_wait(struct pci_doe_mb *doe_mb, unsigned long timeout)
>
> This feels misnamed to me now. It's not waiting for the DOE, it's
> just sleeping unless we cancel. The actual poll / wait is handled
> outside this. pci_doe_sleep_unless_cancel() maybe?
It is waiting a timeout period _or_ checking if we are canceled.
So I think it is correct for the common case.
>
> > +{
> > + if (wait_event_timeout(doe_mb->wq,
> > + test_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags),
> > + timeout))
> > + return -EIO;
> > + return 0;
> > +}
>
> > +static int pci_doe_send_req(struct pci_doe_mb *doe_mb,
> > + struct pci_doe_task *task)
> > +{
> > + struct pci_dev *pdev = doe_mb->pdev;
> > + int offset = doe_mb->cap_offset;
> > + u32 val;
> > + int i;
> > +
> > + /*
> > + * Check the DOE busy bit is not set. If it is set, this could indicate
> > + * someone other than Linux (e.g. firmware) is using the mailbox. Note
> > + * it is expected that firmware and OS will negotiate access rights via
> > + * an, as yet to be defined method.
>
> trivial: an, as yet to be defined, method.
I'll send a follow on patch for this.
>
> > + */
> > + pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
> > + if (FIELD_GET(PCI_DOE_STATUS_BUSY, val))
> > + return -EBUSY;
> > +
> > + if (FIELD_GET(PCI_DOE_STATUS_ERROR, val))
> > + return -EIO;
> > +
> > + /* Write DOE Header */
> > + val = FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_VID, task->prot.vid) |
> > + FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, task->prot.type);
> > + pci_write_config_dword(pdev, offset + PCI_DOE_WRITE, val);
> > + /* Length is 2 DW of header + length of payload in DW */
> > + pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
> > + FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH,
> > + 2 + task->request_pl_sz /
> > + sizeof(u32)));
> > + for (i = 0; i < task->request_pl_sz / sizeof(u32); i++)
> > + pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
> > + task->request_pl[i]);
> > +
> > + pci_doe_write_ctrl(doe_mb, PCI_DOE_CTRL_GO);
> > +
> > + /* Request is sent - now wait for poll or IRQ */
>
> Could drop the IRQ given not currently handling. Though I suppose it's correct
> documentation for this function, so can leave it if preferred.
> More than possible we'll get a follow up patch dropping it though from
> someone doing cleanup.
I send a follow on clean patch for this as well. I suspect IRQ may never make
it in. But for sure it will not for this cycle. Best to have the comment
correct for the final 5.20.
>
> > + return 0;
> > +}
> > +
>
> ...
>
> > +
> > +static void doe_statemachine_work(struct work_struct *work)
> > +{
> > + struct pci_doe_task *task = container_of(work, struct pci_doe_task,
> > + work);
> > + struct pci_doe_mb *doe_mb = task->doe_mb;
> > + struct pci_dev *pdev = doe_mb->pdev;
> > + int offset = doe_mb->cap_offset;
> > + unsigned long timeout_jiffies;
> > + u32 val;
> > + int rc;
> > +
> > + if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags)) {
> > + signal_task_complete(task, -EIO);
> > + return;
> > + }
> > +
> > + /* Send request */
> > + rc = pci_doe_send_req(doe_mb, task);
> > +
> nitpick, but blank line separating call from error handling reduces
> readability in my opinion.
:-/
I'm not sure why I did this. More clean ups.
>
> > + if (rc) {
> > + /*
> > + * The specification does not provide any guidance on how to
> > + * resolve conflicting requests from other entities.
> > + * Furthermore, it is likely that busy will not be detected
> > + * most of the time. Flag any detection of status busy with an
> > + * error.
> > + */
> > + if (rc == -EBUSY)
> > + dev_err_ratelimited(&pdev->dev, "[%x] busy detected; another entity is sending conflicting requests\n",
> > + offset);
> > + signal_task_abort(task, rc);
> > + return;
> > + }
> > +
> > + timeout_jiffies = jiffies + PCI_DOE_TIMEOUT;
> > + rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL);
>
> What's this particular wait for? I think you can just move directly to checking
> if the response is ready.
We could but I assume it will take at least some time to process the request.
So it seemed best to wait and then check.
But of course we all know that also used to wait for an IRQ as an option. :-/
I'm really on the fence here because I don't think it really matters. We are
sleeping so it does not really affect the system much and this is not a
performance path. If we were spinning I would agree with you.
>
> > + if (rc) {
> > + signal_task_abort(task, rc);
> > + return;
> > + }
> > +
> > + /* Poll for response */
> > +retry_resp:
> > + pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val);
> > + if (FIELD_GET(PCI_DOE_STATUS_ERROR, val)) {
> > + signal_task_abort(task, -EIO);
> > + return;
> > + }
> > +
> > + if (!FIELD_GET(PCI_DOE_STATUS_DATA_OBJECT_READY, val)) {
> > + if (time_after(jiffies, timeout_jiffies)) {
> > + signal_task_abort(task, -EIO);
> > + return;
> > + }
> > + rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL);
> > + if (rc) {
> > + signal_task_abort(task, rc);
> > + return;
> > + }
> > + goto retry_resp;
> > + }
> > +
> > + rc = pci_doe_recv_resp(doe_mb, task);
> > + if (rc < 0) {
> > + signal_task_abort(task, rc);
> > + return;
> > + }
> > +
> > + signal_task_complete(task, rc);
> > +}
> > +
>
> > +/**
> > + * pci_doe_supports_prot() - Return if the DOE instance supports the given
> > + * protocol
> > + * @doe_mb: DOE mailbox capability to query
> > + * @vid: Protocol Vendor ID
> > + * @type: Protocol type
> > + *
> > + * RETURNS: True if the DOE mailbox supports the protocol specified
> > + */
> > +bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type)
> > +{
> > + unsigned long index;
> > + void *entry;
> > +
> > + /* The discovery protocol must always be supported */
> > + if (vid == PCI_VENDOR_ID_PCI_SIG && type == PCI_DOE_PROTOCOL_DISCOVERY)
> > + return true;
>
> Given how cheap this look up is now it's all in xarray, we could drop this
> 'optimization'. I'm fairly sure the discovery protocol will always be
> discovered (spec says it must be returned when calling itself as the fist
> protocol).
No we can't because this is called before the xarray is populated with the
discovery protocol. This was actually added not as an optimization but to
allow the discovery protocol to run through the common query path.
>
> > +
> > + xa_for_each(&doe_mb->prots, index, entry)
> > + if (entry == pci_doe_xa_prot_entry(vid, type))
> > + return true;
> > +
> > + return false;
> > +}
> > +EXPORT_SYMBOL_GPL(pci_doe_supports_prot);
>
>
> > +EXPORT_SYMBOL_GPL(pci_doe_submit_task);
> > diff --git a/include/linux/pci-doe.h b/include/linux/pci-doe.h
> > new file mode 100644
> > index 000000000000..c77f6258c996
> > --- /dev/null
> > +++ b/include/linux/pci-doe.h
> > @@ -0,0 +1,79 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Data Object Exchange
> > + * PCIe r6.0, sec 6.30 DOE
> > + *
> > + * Copyright (C) 2021 Huawei
> > + * Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > + *
> > + * Copyright (C) 2022 Intel Corporation
> > + * Ira Weiny <ira.weiny@intel.com>
> > + */
> > +
> > +#ifndef LINUX_PCI_DOE_H
> > +#define LINUX_PCI_DOE_H
> > +
> > +#include <linux/completion.h>
>
> include not needed any more.
Will fix,
Ira
>
> Thanks,
>
> Jonathan
>
> > +
> > +struct pci_doe_protocol {
> > + u16 vid;
> > + u8 type;
> > +};
> > +
> > +struct pci_doe_mb;
> > +
> > +/**
> > + * struct pci_doe_task - represents a single query/response
> > + *
> > + * @prot: DOE Protocol
> > + * @request_pl: The request payload
> > + * @request_pl_sz: Size of the request payload (bytes)
> > + * @response_pl: The response payload
> > + * @response_pl_sz: Size of the response payload (bytes)
> > + * @rv: Return value. Length of received response or error (bytes)
> > + * @complete: Called when task is complete
> > + * @private: Private data for the consumer
> > + * @work: Used internally by the mailbox
> > + * @doe_mb: Used internally by the mailbox
> > + *
> > + * The payload sizes and rv are specified in bytes with the following
> > + * restrictions concerning the protocol.
> > + *
> > + * 1) The request_pl_sz must be a multiple of double words (4 bytes)
> > + * 2) The response_pl_sz must be >= a single double word (4 bytes)
> > + * 3) rv is returned as bytes but it will be a multiple of double words
> > + *
> > + * NOTE there is no need for the caller to initialize work or doe_mb.
> > + */
> > +struct pci_doe_task {
> > + struct pci_doe_protocol prot;
> > + u32 *request_pl;
> > + size_t request_pl_sz;
> > + u32 *response_pl;
> > + size_t response_pl_sz;
> > + int rv;
> > + void (*complete)(struct pci_doe_task *task);
> > + void *private;
> > +
> > + /* No need for the user to initialize these fields */
> > + struct work_struct work;
> > + struct pci_doe_mb *doe_mb;
> > +};
> > +
> > +/**
> > + * pci_doe_for_each_off - Iterate each DOE capability
> > + * @pdev: struct pci_dev to iterate
> > + * @off: u16 of config space offset of each mailbox capability found
> > + */
> > +#define pci_doe_for_each_off(pdev, off) \
> > + for (off = pci_find_next_ext_capability(pdev, off, \
> > + PCI_EXT_CAP_ID_DOE); \
> > + off > 0; \
> > + off = pci_find_next_ext_capability(pdev, off, \
> > + PCI_EXT_CAP_ID_DOE))
> > +
> > +struct pci_doe_mb *pcim_doe_create_mb(struct pci_dev *pdev, u16 cap_offset);
> > +bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type);
> > +int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task);
> > +
> > +#endif
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH V14 0/7] CXL: Read CDAT
2022-07-19 15:21 ` [PATCH V14 0/7] CXL: Read CDAT Jonathan Cameron
@ 2022-07-19 19:23 ` Dan Williams
0 siblings, 0 replies; 20+ messages in thread
From: Dan Williams @ 2022-07-19 19:23 UTC (permalink / raw)
To: Jonathan Cameron, ira.weiny
Cc: Dan Williams, Bjorn Helgaas, Lukas Wunner, Alison Schofield,
Vishal Verma, Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl,
linux-pci
Jonathan Cameron wrote:
> On Thu, 14 Jul 2022 20:04:17 -0700
> ira.weiny@intel.com wrote:
>
> > From: Ira Weiny <ira.weiny@intel.com>
> >
> > Details of changes are in the individual patches.
> >
> > Major changes from V13:[10]
> > Dan minor updates
> > Willy's suggestion of documentation is good but I'm deferring it until
> > we get the location of the PCI mailboxes settled.
> > Drop retry CDAT patch
> > Drop DSMAS patch
> > Rebased on latest cxl-pending
> >
> > CXL drivers need various data which are provided through generic DOE mailboxes
> > as defined in the PCIe 6.0 spec.[1]
> >
> > One such data is the Coherent Device Attribute Table (CDAT). CDAT data provides
> > coherent information about the various devices in the system. It was developed
> > because systems no longer have a priori knowledge of all coherent devices
> > within a system. CDAT describes the coherent characteristics of the
> > components on the CXL bus separate from system configurations. The OS can
> > then, for example, use this information to form correct interleave sets.
> >
> > To begin reading the CDAT the OS must have support to access the DOE mailboxes
> > provided by the CXL devices.
> >
> > Because DOE is not specific to DOE but is provided within the PCI spec, the
> > series adds PCI DOE capability library functions. These functions allow for
> > the iteration of the DOE capabilities on a device as well as creating
> > pci_doe_mb structures which can control the operation of the DOE state machine.
> >
> > For now the iteration of and storage of the DOE mailboxes is done on memdev
> > objects within the CXL stack. When this is needed in more generic code this
> > can be lifted later.
> >
> > This work was tested using qemu.
> >
> > [0] https://lore.kernel.org/linux-cxl/20211105235056.3711389-1-ira.weiny@intel.com/
> > [1] https://pcisig.com/specifications
> > [2] https://lore.kernel.org/qemu-devel/20210202005948.241655-1-ben.widawsky@intel.com/
> > [3] https://lore.kernel.org/linux-cxl/20220201071952.900068-1-ira.weiny@intel.com/
> > [4] https://lore.kernel.org/linux-cxl/20220330235920.2800929-1-ira.weiny@intel.com/
> > [5] https://lore.kernel.org/linux-cxl/20220414203237.2198665-1-ira.weiny@intel.com/
> > [6] https://lore.kernel.org/linux-cxl/20220531152632.1397976-1-ira.weiny@intel.com/
> > [7] https://lore.kernel.org/linux-cxl/20220605005049.2155874-1-ira.weiny@intel.com/
> > [8] https://lore.kernel.org/linux-cxl/20220610202259.3544623-1-ira.weiny@intel.com/
> > [9] https://lore.kernel.org/linux-cxl/20220628041527.742333-1-ira.weiny@intel.com/
> > [10] https://lore.kernel.org/linux-cxl/20220705154932.2141021-1-ira.weiny@intel.com/
> >
> >
> > Previous changes
> > ================
> >
> > Changes from V12:[9]
> > A couple of bug fixes in the new XArray stuff
> > Remove the IRQ support because I did not realize how that worked and it
> > was complicating things.
> > Remove busy retries and replace with an error as there is no good way
> > to ensure it will work.
>
> This is fine for userspace access, but I think we probably will want retries
> once we are using it in kernel. Whilst we'd not expect it to be common as
> per (very late) reply I sent to v13 discussion, the CDAT table can change
> all on it's own (as far as software can see). I'd expect it to be a once in
> a blue moon thing though.
It had better not change outside an explicit remap of the DPA space via
a command like set-partition with the immediate flag set... or maybe
after a firmware update. Anything is just unsupportable and broken and
the vendor of a device that changes the CDAT without the OS asking for
the change gets to keep the pieces.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH V14 3/7] PCI/DOE: Add DOE mailbox support functions
2022-07-19 19:16 ` Ira Weiny
@ 2022-07-19 19:50 ` Ira Weiny
2022-07-20 11:24 ` Jonathan Cameron
1 sibling, 0 replies; 20+ messages in thread
From: Ira Weiny @ 2022-07-19 19:50 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Dan Williams, Bjorn Helgaas, Li, Ming, Bjorn Helgaas,
Matthew Wilcox, Lukas Wunner, Alison Schofield, Vishal Verma,
Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl, linux-pci
On Tue, Jul 19, 2022 at 12:16:06PM -0700, Ira wrote:
> On Tue, Jul 19, 2022 at 05:35:53PM +0100, Jonathan Cameron wrote:
[snip]
> > Hi Ira,
> >
> > Thanks for persisting with this!
> >
> > So, I think this works, but there is at least one 'sleep' I can't
> > see a purpose for. I think it's just a left over from refactoring.
> >
> > A few other more trivial things inline.
[snip]
> > > +
> > > +#define PCI_DOE_BUSY_MAX_RETRIES 16
> > Left over from removed code.
>
> I think Dan may have taken these. If so I'll send a clean up. If not I can
> spin. Let me check.
I'm spinning a v15 of this patch.
[snip]
>
> >
> > > + if (rc) {
> > > + /*
> > > + * The specification does not provide any guidance on how to
> > > + * resolve conflicting requests from other entities.
> > > + * Furthermore, it is likely that busy will not be detected
> > > + * most of the time. Flag any detection of status busy with an
> > > + * error.
> > > + */
> > > + if (rc == -EBUSY)
> > > + dev_err_ratelimited(&pdev->dev, "[%x] busy detected; another entity is sending conflicting requests\n",
> > > + offset);
> > > + signal_task_abort(task, rc);
> > > + return;
> > > + }
> > > +
> > > + timeout_jiffies = jiffies + PCI_DOE_TIMEOUT;
> > > + rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL);
> >
> > What's this particular wait for? I think you can just move directly to checking
> > if the response is ready.
>
> We could but I assume it will take at least some time to process the request.
> So it seemed best to wait and then check.
>
> But of course we all know that also used to wait for an IRQ as an option. :-/
>
> I'm really on the fence here because I don't think it really matters. We are
> sleeping so it does not really affect the system much and this is not a
> performance path. If we were spinning I would agree with you.
I've deferred to your expertise here and removed the extra wait.
Ira
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH V14 3/7] PCI/DOE: Add DOE mailbox support functions
2022-07-19 19:16 ` Ira Weiny
2022-07-19 19:50 ` Ira Weiny
@ 2022-07-20 11:24 ` Jonathan Cameron
1 sibling, 0 replies; 20+ messages in thread
From: Jonathan Cameron @ 2022-07-20 11:24 UTC (permalink / raw)
To: Ira Weiny
Cc: Dan Williams, Bjorn Helgaas, Li, Ming, Bjorn Helgaas,
Matthew Wilcox, Lukas Wunner, Alison Schofield, Vishal Verma,
Dave Jiang, Ben Widawsky, linux-kernel, linux-cxl, linux-pci
On Tue, 19 Jul 2022 12:16:06 -0700
Ira Weiny <ira.weiny@intel.com> wrote:
> On Tue, Jul 19, 2022 at 05:35:53PM +0100, Jonathan Cameron wrote:
> > On Thu, 14 Jul 2022 20:04:20 -0700
> > ira.weiny@intel.com wrote:
> >
> > > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > >
> > > Introduced in a PCIe r6.0, sec 6.30, DOE provides a config space based
> > > mailbox with standard protocol discovery. Each mailbox is accessed
> > > through a DOE Extended Capability.
> > >
> > > Each DOE mailbox must support the DOE discovery protocol in addition to
> > > any number of additional protocols.
> > >
> > > Define core PCIe functionality to manage a single PCIe DOE mailbox at a
> > > defined config space offset. Functionality includes iterating,
> > > creating, query of supported protocol, and task submission. Destruction
> > > of the mailboxes is device managed.
> > >
> > > Cc: "Li, Ming" <ming4.li@intel.com>
> > > Cc: Bjorn Helgaas <helgaas@kernel.org>
> > > Cc: Matthew Wilcox <willy@infradead.org>
> > > Acked-by: Bjorn Helgaas <helgaas@kernel.org>
> > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > Co-developed-by: Ira Weiny <ira.weiny@intel.com>
> > > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> > Hi Ira,
> >
> > Thanks for persisting with this!
> >
> > So, I think this works, but there is at least one 'sleep' I can't
> > see a purpose for. I think it's just a left over from refactoring.
> >
> > A few other more trivial things inline.
> >
> > Thanks,
> >
> > Jonathan
> >
> >
> > >
> > >> # Endpoint library must be initialized before its users
> > > obj-$(CONFIG_PCI_ENDPOINT) += endpoint/
> > > diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c
> > > new file mode 100644
> > > index 000000000000..12c3762be22f
> > > --- /dev/null
> > > +++ b/drivers/pci/doe.c
> > > @@ -0,0 +1,546 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Data Object Exchange
> > > + * PCIe r6.0, sec 6.30 DOE
> > > + *
> > > + * Copyright (C) 2021 Huawei
> > > + * Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > + *
> > > + * Copyright (C) 2022 Intel Corporation
> > > + * Ira Weiny <ira.weiny@intel.com>
> > > + */
> > > +
> > > +#define dev_fmt(fmt) "DOE: " fmt
> > > +
> > > +#include <linux/bitfield.h>
> > > +#include <linux/delay.h>
> > > +#include <linux/jiffies.h>
> > > +#include <linux/mutex.h>
> > > +#include <linux/pci.h>
> > > +#include <linux/pci-doe.h>
> > > +#include <linux/workqueue.h>
> > > +
> > > +#define PCI_DOE_PROTOCOL_DISCOVERY 0
> > > +
> > > +#define PCI_DOE_BUSY_MAX_RETRIES 16
> > Left over from removed code.
>
> I think Dan may have taken these. If so I'll send a clean up. If not I can
> spin. Let me check.
>
Absolutely. All tiny improvements, so fine to go in next cycle given late timing.
> > > +/**
> > > + * pci_doe_supports_prot() - Return if the DOE instance supports the given
> > > + * protocol
> > > + * @doe_mb: DOE mailbox capability to query
> > > + * @vid: Protocol Vendor ID
> > > + * @type: Protocol type
> > > + *
> > > + * RETURNS: True if the DOE mailbox supports the protocol specified
> > > + */
> > > +bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type)
> > > +{
> > > + unsigned long index;
> > > + void *entry;
> > > +
> > > + /* The discovery protocol must always be supported */
> > > + if (vid == PCI_VENDOR_ID_PCI_SIG && type == PCI_DOE_PROTOCOL_DISCOVERY)
> > > + return true;
> >
> > Given how cheap this look up is now it's all in xarray, we could drop this
> > 'optimization'. I'm fairly sure the discovery protocol will always be
> > discovered (spec says it must be returned when calling itself as the fist
> > protocol).
>
> No we can't because this is called before the xarray is populated with the
> discovery protocol. This was actually added not as an optimization but to
> allow the discovery protocol to run through the common query path.
>
Ah. I was too lazy to check if that was the case :)
Jonathan
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-07-20 11:24 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-15 3:04 [PATCH V14 0/7] CXL: Read CDAT ira.weiny
2022-07-15 3:04 ` [PATCH V14 1/7] PCI: Add vendor ID for the PCI SIG ira.weiny
2022-07-15 3:04 ` [PATCH V14 2/7] PCI: Replace magic constant for PCI Sig Vendor ID ira.weiny
2022-07-15 3:04 ` [PATCH V14 3/7] PCI/DOE: Add DOE mailbox support functions ira.weiny
2022-07-19 16:35 ` Jonathan Cameron
2022-07-19 19:16 ` Ira Weiny
2022-07-19 19:50 ` Ira Weiny
2022-07-20 11:24 ` Jonathan Cameron
2022-07-15 3:04 ` [PATCH V14 4/7] cxl/pci: Create PCI DOE mailbox's for memory devices ira.weiny
2022-07-19 16:38 ` Jonathan Cameron
2022-07-15 3:04 ` [PATCH V14 5/7] driver-core: Introduce BIN_ATTR_ADMIN_{RO,RW} ira.weiny
2022-07-19 16:39 ` Jonathan Cameron
2022-07-15 3:04 ` [PATCH V14 6/7] cxl/port: Read CDAT table ira.weiny
2022-07-16 3:27 ` Dan Williams
2022-07-19 1:19 ` Dan Williams
2022-07-15 3:04 ` [PATCH V14 7/7] cxl/port: Introduce cxl_cdat_valid() ira.weiny
2022-07-16 2:26 ` Dan Williams
2022-07-19 16:47 ` Jonathan Cameron
2022-07-19 15:21 ` [PATCH V14 0/7] CXL: Read CDAT Jonathan Cameron
2022-07-19 19:23 ` Dan Williams
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