From: Vidya Sagar <vidyas@nvidia.com>
To: <bhelgaas@google.com>, <lpieralisi@kernel.org>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
Cc: <kw@linux.com>, <kishon@ti.com>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
<sagar.tv@gmail.com>
Subject: [PATCH V6 10/16] PCI: tegra194: Fix root port interrupt handling
Date: Thu, 21 Jul 2022 19:50:46 +0530 [thread overview]
Message-ID: <20220721142052.25971-11-vidyas@nvidia.com> (raw)
In-Reply-To: <20220721142052.25971-1-vidyas@nvidia.com>
As part of root port interrupt handling, level-0 register is read
first and based on the bits set in that, corresponding level-1 registers
are read for further interrupt processing. Since both these values are
currently read into the same 'val' variable, checking level-0 bits the
second time around is happening on the 'val' variable value of level-1
register contents instead of freshly reading the level-0 value again.
This is fixed by using different variables to store level-0 and level-1
registers contents.
Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V6:
* New addition in V6 based on Bjorn's review comment
drivers/pci/controller/dwc/pcie-tegra194.c | 46 +++++++++++-----------
1 file changed, 22 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 6f890453021d..23377425952a 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -338,15 +338,14 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
struct tegra_pcie_dw *pcie = arg;
struct dw_pcie *pci = &pcie->pci;
struct pcie_port *pp = &pci->pp;
- u32 val, tmp;
+ u32 val, status_l0, status_l1;
u16 val_w;
- val = appl_readl(pcie, APPL_INTR_STATUS_L0);
- if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
- val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
- if (val & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) {
- appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0);
-
+ status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
+ if (status_l0 & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
+ status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
+ appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
+ if (status_l1 & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) {
/* SBR & Surprise Link Down WAR */
val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
@@ -362,15 +361,15 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
}
}
- if (val & APPL_INTR_STATUS_L0_INT_INT) {
- val = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
- if (val & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) {
+ if (status_l0 & APPL_INTR_STATUS_L0_INT_INT) {
+ status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
+ if (status_l1 & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) {
appl_writel(pcie,
APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS,
APPL_INTR_STATUS_L1_8_0);
apply_bad_link_workaround(pp);
}
- if (val & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) {
+ if (status_l1 & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) {
appl_writel(pcie,
APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS,
APPL_INTR_STATUS_L1_8_0);
@@ -382,25 +381,24 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
}
}
- val = appl_readl(pcie, APPL_INTR_STATUS_L0);
- if (val & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) {
- val = appl_readl(pcie, APPL_INTR_STATUS_L1_18);
- tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
- if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) {
+ if (status_l0 & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) {
+ status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_18);
+ val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
+ if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) {
dev_info(pci->dev, "CDM check complete\n");
- tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE;
+ val |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE;
}
- if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) {
+ if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) {
dev_err(pci->dev, "CDM comparison mismatch\n");
- tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR;
+ val |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR;
}
- if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) {
+ if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) {
dev_err(pci->dev, "CDM Logic error\n");
- tmp |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR;
+ val |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR;
}
- dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, tmp);
- tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR);
- dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", tmp);
+ dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR);
+ dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", val);
}
return IRQ_HANDLED;
--
2.17.1
next prev parent reply other threads:[~2022-07-21 14:23 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-21 14:20 [PATCH V6 00/16] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
2022-07-21 14:20 ` [PATCH V6 01/16] dt-bindings: pci: tegra: Convert to json-schema Vidya Sagar
2022-07-21 14:20 ` [PATCH V6 02/16] dt-bindings: PCI: tegra234: Add schema for tegra234 rootport mode Vidya Sagar
2022-07-21 14:20 ` [PATCH V6 03/16] dt-bindings: PCI: tegra234: Add schema for tegra234 endpoint mode Vidya Sagar
2022-07-21 14:20 ` [PATCH V6 04/16] arm64: tegra: Add regulators required for PCIe Vidya Sagar
2022-07-21 14:20 ` [PATCH V6 05/16] arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT Vidya Sagar
2022-07-21 14:20 ` [PATCH V6 06/16] arm64: tegra: Enable PCIe slots in P3737-0000 board Vidya Sagar
2022-07-21 14:20 ` [PATCH V6 07/16] PCI: Disable MSI for Tegra234 root ports Vidya Sagar
2022-07-21 14:20 ` [PATCH V6 08/16] Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie" Vidya Sagar
2022-07-21 14:20 ` [PATCH V6 09/16] PCI: tegra194: Find RAS DES PCIe capability offset Vidya Sagar
2022-07-21 14:20 ` Vidya Sagar [this message]
2022-07-21 14:20 ` [PATCH V6 11/16] PCI: tegra194: Clear bandwidth management status Vidya Sagar
2022-07-21 14:20 ` [PATCH V6 12/16] PCI: tegra194: Enable support for 256 Byte payload Vidya Sagar
2022-07-21 14:20 ` [PATCH V6 13/16] PCI: tegra194: Cleanup the exit path for endpoint mode Vidya Sagar
2022-07-21 14:20 ` [PATCH V6 14/16] PCI: tegra194: Fix link up retry sequence Vidya Sagar
2022-07-22 21:54 ` Rob Herring
2022-07-21 14:20 ` [PATCH V6 15/16] PCI: tegra194: Extend endpoint mode support Vidya Sagar
2022-07-21 14:20 ` [PATCH V6 16/16] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
2022-07-22 22:17 ` [PATCH V6 00/16] " Bjorn Helgaas
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