From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3234AC43334 for ; Sun, 24 Jul 2022 08:25:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231558AbiGXIZ0 (ORCPT ); Sun, 24 Jul 2022 04:25:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230421AbiGXIZN (ORCPT ); Sun, 24 Jul 2022 04:25:13 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A2565FC9 for ; Sun, 24 Jul 2022 01:25:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658651110; x=1690187110; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pDRjkbFnNU7Vmo4YrYOSma2uS6k6jU4Vhpzxe//uSfc=; b=FZ4IsK08aF8FbTxkfBg+AhfdJvFykwQt67W2tDrWLRLBJf/xxYgWNIrv 30qgumZ8uZKDzUeXsN2GENN1TLw2eIg96Vxoj9qCkDUL9+DHZvC5kXzfW VC8rm424mU1OChj5dPnYtEp0n3jkbXjzJU4Y9ejSolcLxbFAD2g3Xp4AB sbX2IxnQ2tEP5O8Z2h2F9F+HE+dJgfIbslN2l4rNSmMUbCI+wcSm/DZdr QR50tBolZcW5EmtJD7B7d52FTp+8te3SDisul8O54QkZfHCfR1Xjb8QWv U1ECNC8g5EoscN1q5gYmypzb5Oq4XDFWUQ+Uhz/qoHnRS+ZY/E0e0B4ft g==; X-IronPort-AV: E=McAfee;i="6400,9594,10417"; a="313267983" X-IronPort-AV: E=Sophos;i="5.93,190,1654585200"; d="scan'208";a="313267983" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jul 2022 01:25:02 -0700 X-IronPort-AV: E=Sophos;i="5.93,190,1654585200"; d="scan'208";a="657756242" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jul 2022 01:24:59 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart Subject: [PATCH v6 04/14] drm/i915/gsc: add GSC XeHP SDV platform definition Date: Sun, 24 Jul 2022 11:24:18 +0300 Message-Id: <20220724082428.218628-5-tomas.winkler@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220724082428.218628-1-tomas.winkler@intel.com> References: <20220724082428.218628-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexander Usyskin Define GSC on XeHP SDV (Intel(R) dGPU without display) XeHP SDV uses the same hardware settings as DG1, but uses polling instead of interrupts and runs the firmware in slow pace due to hardware limitations. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c index f963c220bbff..bfc307e49bf9 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = { } }; +static const struct gsc_def gsc_def_xehpsdv[] = { + { + /* HECI1 not enabled on the device. */ + }, + { + .name = "mei-gscfi", + .bar = DG1_GSC_HECI2_BASE, + .bar_size = GSC_BAR_LENGTH, + .use_polling = true, + .slow_fw = true, + } +}; + static const struct gsc_def gsc_def_dg2[] = { { .name = "mei-gsc", @@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915, if (IS_DG1(i915)) { def = &gsc_def_dg1[intf_id]; + } else if (IS_XEHPSDV(i915)) { + def = &gsc_def_xehpsdv[intf_id]; } else if (IS_DG2(i915)) { def = &gsc_def_dg2[intf_id]; } else { -- 2.35.3