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From: "Maíra Canal" <mairacanal@riseup.net>
To: Harry Wentland <harry.wentland@amd.com>,
	Leo Li <sunpeng.li@amd.com>,
	Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>,
	Alex Deucher <alexander.deucher@amd.com>,
	christian.koenig@amd.com, Xinhui.Pan@amd.com,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>
Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	mwen@igalia.com, andrealmeid@riseup.net,
	"Isabella Basso" <isabbasso@riseup.net>,
	magalilemes00@gmail.com, tales.aparecida@gmail.com,
	"Maíra Canal" <mairacanal@riseup.net>
Subject: [PATCH 03/16] drm/amd/display: Remove DSCCLK_calculated VBA variable
Date: Thu, 28 Jul 2022 15:20:35 -0300	[thread overview]
Message-ID: <20220728182047.264825-4-mairacanal@riseup.net> (raw)
In-Reply-To: <20220728182047.264825-1-mairacanal@riseup.net>

The DSCCLK_calculated variable from the struct vba_vars_st is
only used on assignments, so its value is not used on code. Moreover,
its getter function is not used also. So, remove the DSCCLK_calculated
entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 .../dc/dml/dcn20/display_mode_vba_20.c        | 21 ++----------------
 .../dc/dml/dcn20/display_mode_vba_20v2.c      | 21 ++----------------
 .../dc/dml/dcn21/display_mode_vba_21.c        | 18 +--------------
 .../dc/dml/dcn30/display_mode_vba_30.c        | 19 ++--------------
 .../dc/dml/dcn31/display_mode_vba_31.c        | 19 ++--------------
 .../dc/dml/dcn314/display_mode_vba_314.c      | 19 ++--------------
 .../dc/dml/dcn32/display_mode_vba_32.c        | 22 ++-----------------
 .../drm/amd/display/dc/dml/display_mode_vba.c |  1 -
 .../drm/amd/display/dc/dml/display_mode_vba.h |  2 --
 9 files changed, 13 insertions(+), 129 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 8a499f8066b7..37a8b418a24d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -1770,28 +1770,11 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
 
 	// DSCCLK
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
-			mode_lib->vba.DSCCLK_calculated[k] = 0.0;
-		} else {
-			if (mode_lib->vba.OutputFormat[k] == dm_420
-					|| mode_lib->vba.OutputFormat[k] == dm_n422)
+		if ((mode_lib->vba.BlendingAndTiming[k] == k) || mode_lib->vba.DSCEnabled[k]) {
+			if (mode_lib->vba.OutputFormat[k] == dm_420 || mode_lib->vba.OutputFormat[k] == dm_n422)
 				mode_lib->vba.DSCFormatFactor = 2;
 			else
 				mode_lib->vba.DSCFormatFactor = 1;
-			if (mode_lib->vba.ODMCombineEnabled[k])
-				mode_lib->vba.DSCCLK_calculated[k] =
-						mode_lib->vba.PixelClockBackEnd[k] / 6
-								/ mode_lib->vba.DSCFormatFactor
-								/ (1
-										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-												/ 100);
-			else
-				mode_lib->vba.DSCCLK_calculated[k] =
-						mode_lib->vba.PixelClockBackEnd[k] / 3
-								/ mode_lib->vba.DSCFormatFactor
-								/ (1
-										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-												/ 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index ef7f0b8ed2d5..0e0697326717 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -1806,28 +1806,11 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
 
 	// DSCCLK
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
-			mode_lib->vba.DSCCLK_calculated[k] = 0.0;
-		} else {
-			if (mode_lib->vba.OutputFormat[k] == dm_420
-					|| mode_lib->vba.OutputFormat[k] == dm_n422)
+		if ((mode_lib->vba.BlendingAndTiming[k] == k) || mode_lib->vba.DSCEnabled[k]) {
+			if (mode_lib->vba.OutputFormat[k] == dm_420 || mode_lib->vba.OutputFormat[k] == dm_n422)
 				mode_lib->vba.DSCFormatFactor = 2;
 			else
 				mode_lib->vba.DSCFormatFactor = 1;
-			if (mode_lib->vba.ODMCombineEnabled[k])
-				mode_lib->vba.DSCCLK_calculated[k] =
-						mode_lib->vba.PixelClockBackEnd[k] / 6
-								/ mode_lib->vba.DSCFormatFactor
-								/ (1
-										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-												/ 100);
-			else
-				mode_lib->vba.DSCCLK_calculated[k] =
-						mode_lib->vba.PixelClockBackEnd[k] / 3
-								/ mode_lib->vba.DSCFormatFactor
-								/ (1
-										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-												/ 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index 8a7485e21d53..aa752d78308f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -1764,28 +1764,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 
 	// DSCCLK
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
-			locals->DSCCLK_calculated[k] = 0.0;
-		} else {
+		if ((mode_lib->vba.BlendingAndTiming[k] == k) || mode_lib->vba.DSCEnabled[k]) {
 			if (mode_lib->vba.OutputFormat[k] == dm_420
 					|| mode_lib->vba.OutputFormat[k] == dm_n422)
 				mode_lib->vba.DSCFormatFactor = 2;
 			else
 				mode_lib->vba.DSCFormatFactor = 1;
-			if (mode_lib->vba.ODMCombineEnabled[k])
-				locals->DSCCLK_calculated[k] =
-						mode_lib->vba.PixelClockBackEnd[k] / 6
-								/ mode_lib->vba.DSCFormatFactor
-								/ (1
-										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-												/ 100);
-			else
-				locals->DSCCLK_calculated[k] =
-						mode_lib->vba.PixelClockBackEnd[k] / 3
-								/ mode_lib->vba.DSCFormatFactor
-								/ (1
-										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-												/ 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 876b321b30ca..cc9b6497b287 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -2159,26 +2159,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 
 	// DSCCLK
 	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
-		if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
-			v->DSCCLK_calculated[k] = 0.0;
-		} else {
-			if (v->OutputFormat[k] == dm_420)
-				v->DSCFormatFactor = 2;
-			else if (v->OutputFormat[k] == dm_444)
-				v->DSCFormatFactor = 1;
-			else if (v->OutputFormat[k] == dm_n422)
+		if ((v->BlendingAndTiming[k] == k) || v->DSCEnabled[k]) {
+			if (v->OutputFormat[k] == dm_420 || v->OutputFormat[k] == dm_n422)
 				v->DSCFormatFactor = 2;
 			else
 				v->DSCFormatFactor = 1;
-			if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12
-					/ v->DSCFormatFactor / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6
-					/ v->DSCFormatFactor / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3
-					/ v->DSCFormatFactor / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 3fab19134480..55ab4ec8b8fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -2286,26 +2286,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 
 	// DSCCLK
 	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
-		if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
-			v->DSCCLK_calculated[k] = 0.0;
-		} else {
-			if (v->OutputFormat[k] == dm_420)
-				v->DSCFormatFactor = 2;
-			else if (v->OutputFormat[k] == dm_444)
-				v->DSCFormatFactor = 1;
-			else if (v->OutputFormat[k] == dm_n422)
+		if ((v->BlendingAndTiming[k] == k) || v->DSCEnabled[k]) {
+			if (v->OutputFormat[k] == dm_420 || v->OutputFormat[k] == dm_n422)
 				v->DSCFormatFactor = 2;
 			else
 				v->DSCFormatFactor = 1;
-			if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
-						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
-						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
-						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index fc4d7474c111..279ed038a359 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -2310,26 +2310,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 
 	// DSCCLK
 	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
-		if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
-			v->DSCCLK_calculated[k] = 0.0;
-		} else {
-			if (v->OutputFormat[k] == dm_420)
-				v->DSCFormatFactor = 2;
-			else if (v->OutputFormat[k] == dm_444)
-				v->DSCFormatFactor = 1;
-			else if (v->OutputFormat[k] == dm_n422)
+		if ((v->BlendingAndTiming[k] == k) || v->DSCEnabled[k]) {
+			if (v->OutputFormat[k] == dm_420 || v->OutputFormat[k] == dm_n422)
 				v->DSCFormatFactor = 2;
 			else
 				v->DSCFormatFactor = 1;
-			if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
-						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
-						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
-						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index a1fb2d1d1cdb..f199ef475ed0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -332,29 +332,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 
 	// DSCCLK
 	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
-		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
-			v->DSCCLK_calculated[k] = 0.0;
-		} else {
-			if (mode_lib->vba.OutputFormat[k] == dm_420)
-				mode_lib->vba.DSCFormatFactor = 2;
-			else if (mode_lib->vba.OutputFormat[k] == dm_444)
-				mode_lib->vba.DSCFormatFactor = 1;
-			else if (mode_lib->vba.OutputFormat[k] == dm_n422)
+		if ((mode_lib->vba.BlendingAndTiming[k] == k) || mode_lib->vba.DSCEnabled[k]) {
+			if (mode_lib->vba.OutputFormat[k] == dm_420 || mode_lib->vba.OutputFormat[k] == dm_n422)
 				mode_lib->vba.DSCFormatFactor = 2;
 			else
 				mode_lib->vba.DSCFormatFactor = 1;
-			if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
-				v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 12
-						/ mode_lib->vba.DSCFormatFactor
-						/ (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
-				v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 6
-						/ mode_lib->vba.DSCFormatFactor
-						/ (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else
-				v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 3
-						/ mode_lib->vba.DSCFormatFactor
-						/ (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index d1c720b48b0c..316153ece160 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -134,7 +134,6 @@ dml_get_attr_func(unbounded_request_enabled, mode_lib->vba.UnboundedRequestEnabl
 
 dml_get_pipe_attr_func(dsc_delay, mode_lib->vba.DSCDelay);
 dml_get_pipe_attr_func(dppclk_calculated, mode_lib->vba.DPPCLK_calculated);
-dml_get_pipe_attr_func(dscclk_calculated, mode_lib->vba.DSCCLK_calculated);
 dml_get_pipe_attr_func(min_ttu_vblank, mode_lib->vba.MinTTUVBlank);
 dml_get_pipe_attr_func(min_ttu_vblank_in_us, mode_lib->vba.MinTTUVBlank);
 dml_get_pipe_attr_func(vratio_prefetch_l, mode_lib->vba.VRatioPrefetchY);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 632041cf49bb..1b037e74bfc3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -73,7 +73,6 @@ dml_get_attr_decl(unbounded_request_enabled);
 
 dml_get_pipe_attr_decl(dsc_delay);
 dml_get_pipe_attr_decl(dppclk_calculated);
-dml_get_pipe_attr_decl(dscclk_calculated);
 dml_get_pipe_attr_decl(min_ttu_vblank);
 dml_get_pipe_attr_decl(min_ttu_vblank_in_us);
 dml_get_pipe_attr_decl(vratio_prefetch_l);
@@ -1033,7 +1032,6 @@ struct vba_vars_st {
 	double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
 	double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
 	double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
-	double DSCCLK_calculated[DC__NUM_DPP__MAX];
 	unsigned int DSCDelay[DC__NUM_DPP__MAX];
 	unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
 	double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
-- 
2.37.1


  parent reply	other threads:[~2022-07-28 18:22 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-28 18:20 [PATCH 00/16] Remove entries from struct vba_vars_st Maíra Canal
2022-07-28 18:20 ` [PATCH 01/16] drm/amd/display: Remove NonUrgentLatencyTolerance VBA variable Maíra Canal
2022-07-28 18:20 ` [PATCH 02/16] drm/amd/display: Remove CompBufReservedSpace* " Maíra Canal
2022-07-28 18:20 ` Maíra Canal [this message]
2022-07-28 18:20 ` [PATCH 04/16] drm/amd/display: Remove AllowDRAMSelfRefreshDuringVBlank " Maíra Canal
2022-07-28 18:20 ` [PATCH 05/16] drm/amd/display: Remove VStartupMargin and FirstMainPlane VBA variables Maíra Canal
2022-07-28 18:20 ` [PATCH 06/16] drm/amd/display: Remove ImmediateFlipSupportedSurface VBA variable Maíra Canal
2022-07-28 18:20 ` [PATCH 07/16] drm/amd/display: Remove WritebackAllowFCLKChangeEndPosition " Maíra Canal
2022-07-28 18:20 ` [PATCH 08/16] drm/amd/display: Remove some XFC variables from VBA Maíra Canal
2022-07-28 18:20 ` [PATCH 09/16] drm/amd/display: Remove SwathWidthCSingleDPP VBA variable Maíra Canal
2022-07-28 18:20 ` [PATCH 10/16] drm/amd/display: Remove ModeIsSupported " Maíra Canal
2022-07-28 18:20 ` [PATCH 11/16] drm/amd/display: Remove MPCCombineEnable " Maíra Canal
2022-07-28 18:20 ` [PATCH 12/16] drm/amd/display: Remove NumberOfDP2p0Support " Maíra Canal
2022-07-28 18:20 ` [PATCH 13/16] drm/amd/display: Remove TFinalxFill " Maíra Canal
2022-07-28 18:20 ` [PATCH 14/16] drm/amd/display: Remove MaximumDCCCompressionYSurface " Maíra Canal
2022-07-28 20:05 ` [PATCH 15/16] drm/amd/display: Remove only mencioned once VBA variables Maíra Canal
2022-07-28 20:06 ` [PATCH 16/16] drm/amd/display: Remove never used " Maíra Canal

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