From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C721C00140 for ; Fri, 5 Aug 2022 09:00:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240242AbiHEJAZ (ORCPT ); Fri, 5 Aug 2022 05:00:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234392AbiHEJAW (ORCPT ); Fri, 5 Aug 2022 05:00:22 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D317B1D5; Fri, 5 Aug 2022 02:00:19 -0700 (PDT) Received: from droid06.amlogic.com (10.18.11.248) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.9; Fri, 5 Aug 2022 17:00:17 +0800 From: Yu Tu To: , , , , , Rob Herring , Neil Armstrong , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Martin Blumenstingl CC: Yu Tu Subject: [PATCH V3 5/6] arm64: dts: meson: add S4 Soc Peripheral clock controller in DT Date: Fri, 5 Aug 2022 16:57:15 +0800 Message-ID: <20220805085716.5635-6-yu.tu@amlogic.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220805085716.5635-1-yu.tu@amlogic.com> References: <20220805085716.5635-1-yu.tu@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.18.11.248] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Added information about the S4 SOC Peripheral Clock controller in DT. Signed-off-by: Yu Tu --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index a816b1f7694b..71be1dda15a2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -6,6 +6,8 @@ #include #include #include +#include +#include / { cpus { @@ -100,6 +102,30 @@ clkc_pll: pll-clock-controller@8000 { #clock-cells = <1>; }; + clkc_periphs: periphs-clock-controller { + compatible = "amlogic,s4-periphs-clkc"; + reg = <0x0 0x0 0x0 0x49c>; + clocks = <&clkc_pll CLKID_FCLK_DIV2>, + <&clkc_pll CLKID_FCLK_DIV2P5>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_FCLK_DIV4>, + <&clkc_pll CLKID_FCLK_DIV5>, + <&clkc_pll CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_HIFI_PLL>, + <&clkc_pll CLKID_GP0_PLL>, + <&clkc_pll CLKID_MPLL0>, + <&clkc_pll CLKID_MPLL1>, + <&clkc_pll CLKID_MPLL2>, + <&clkc_pll CLKID_MPLL3>, + <&clkc_pll CLKID_HDMI_PLL>, + <&xtal>; + clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", + "fclk_div4", "fclk_div5", "fclk_div7", + "hifi_pll", "gp0_pll", "mpll0", "mpll1", + "mpll2", "mpll3", "hdmi_pll", "xtal"; + #clock-cells = <1>; + }; + periphs_pinctrl: pinctrl@4000 { compatible = "amlogic,meson-s4-periphs-pinctrl"; #address-cells = <2>; -- 2.33.1