From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7C0BC00140 for ; Mon, 15 Aug 2022 15:32:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232327AbiHOPc4 (ORCPT ); Mon, 15 Aug 2022 11:32:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233115AbiHOPc1 (ORCPT ); Mon, 15 Aug 2022 11:32:27 -0400 Received: from wout2-smtp.messagingengine.com (wout2-smtp.messagingengine.com [64.147.123.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46EFF1705C; Mon, 15 Aug 2022 08:32:12 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id 55DA43200903; Mon, 15 Aug 2022 11:32:10 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Mon, 15 Aug 2022 11:32:11 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h=cc :cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm3; t=1660577529; x= 1660663929; bh=0H1FgCTKGm4EwtAlZfdPc/4yY1n4HBSyRugi/OIJS9g=; b=i s9Pwq361itx3Jtl4ywNGvG4TAFsd8iXDpwLJ432J/j4IADTZDWxuIXWPHZwNi7JN up+cvVK3NC7bE8d8l0o8b2500uYnSrfJEojLWvn+zdXZOZlU8u5iUnkCLSh/alL2 s9QB/Bxy/56V9lSIRpvuBkUa6sNR3+VERlTJelHIiamdCzzygWmj0uMtK15B451q oFwQvQ/XZ8LGDFx9tOwGJEA5EmGYXQ9EHm6D+6ZP2/a1wHfYvra8S+ldrNgRBI2j zfKQVhYk5A7cS/w68HHNqOPQvADiLAHC00VvKH7hVlqlCy7wa1jwO++fBqMpfLO1 z2tNIgZXEuypOzW85LaeQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1660577529; x= 1660663929; bh=0H1FgCTKGm4EwtAlZfdPc/4yY1n4HBSyRugi/OIJS9g=; b=2 W6J17YR5uDpGSKqt9GFekVnfOcJFfWut+dzg+fA4476CEUV9qMiVh1AkVNG6ELfF fPsrY2HgOECI7TFitRnxPS6YJbtLidgUoetIQhj4a3y5ArDSOXvzCInGj58oDKmz mLMp1tsDls/5EorXa+eVc79vSqSYNq7j9CintlCVx2w/2QpZ2tGSsCYYuHdTxN5S rFmbbThNsd7yPKbhdVMBCNgolEHqbLfF9ySBvnn+cwWuqpN5po2iTR1TLcHjpt0U 7FmaJdL4kM1QwyoIf9Cq3G3SrF9rxlrp7gctu2aVVi1Q0gxjQZIcH7JDkcpUDo/U nJO4hnwhd9XF15kJqA4Jg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrvdehvddgledtucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhggtgfogfesthekredtredtjeenucfhrhhomhepofgr gihimhgvucftihhprghrugcuoehmrgigihhmvgestggvrhhnohdrthgvtghhqeenucggtf frrghtthgvrhhnpefgfffgteffuddulefhveeiffffudelvefggeekueetgfffjeehleel keejfefhjeenucevlhhushhtvghrufhiiigvpedunecurfgrrhgrmhepmhgrihhlfhhroh hmpehmrgigihhmvgestggvrhhnohdrthgvtghh X-ME-Proxy: Feedback-ID: i8771445c:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 15 Aug 2022 11:32:09 -0400 (EDT) From: Maxime Ripard To: Michael Turquette , Ray Jui , Broadcom internal kernel review list , Florian Fainelli , David Airlie , Daniel Vetter , Stephen Boyd , Scott Branden , Maxime Ripard , Emma Anholt Cc: Maxime Ripard , linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, Dom Cobley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 7/7] drm/vc4: Make sure we don't end up with a core clock too high Date: Mon, 15 Aug 2022 17:31:29 +0200 Message-Id: <20220815-rpi-fix-4k-60-v1-7-c52bd642f7c6@cerno.tech> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815-rpi-fix-4k-60-v1-0-c52bd642f7c6@cerno.tech> References: <20220815-rpi-fix-4k-60-v1-0-c52bd642f7c6@cerno.tech> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.10.0-dev-a76f5 X-Developer-Signature: v=1; a=openpgp-sha256; l=2484; i=maxime@cerno.tech; h=from:subject:message-id; bh=5xL8zqAbx64ymg/R2TZazkdU4kRqZkVFXJuXP1IVv7A=; b=owGbwMvMwCX2+D1vfrpE4FHG02pJDEm/0k5YZt2yOnqh5LT2jrYtu/bzGz9g4Aq+HREa9zL+wjHv nWvsO0pZGMS4GGTFFFlihM2XxJ2a9bqTjW8ezBxWJpAhDFycAjCR5ixGhu2p88p/tNU+SEpdLytQWJ 6RpddvzDMjOW3znZtihvwzixgZTrJItM8969r9Q2jjhHlvv/Td2bTt4hPV9F9ZXMd7bqnE8QEA X-Developer-Key: i=maxime@cerno.tech; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Following the clock rate range improvements to the clock framework, trying to set a disjoint range on a clock will now result in an error. Thus, we can't set a minimum rate higher than the maximum reported by the firmware, or clk_set_min_rate() will fail. Thus we need to clamp the rate we are about to ask for to the maximum rate possible on that clock. Signed-off-by: Maxime Ripard diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c index b45dcdfd7306..4794e7235bb0 100644 --- a/drivers/gpu/drm/vc4/vc4_kms.c +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -22,6 +22,8 @@ #include #include +#include + #include "vc4_drv.h" #include "vc4_regs.h" @@ -354,6 +356,7 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state) struct vc4_hvs_state *new_hvs_state; struct drm_crtc *crtc; struct vc4_hvs_state *old_hvs_state; + unsigned long max_clock_rate; unsigned int channel; int i; @@ -394,11 +397,12 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state) old_hvs_state->fifo_state[channel].pending_commit = NULL; } + max_clock_rate = rpi_firmware_clk_get_max_rate(hvs->core_clk); if (vc4->is_vc5) { unsigned long state_rate = max(old_hvs_state->core_clock_rate, new_hvs_state->core_clock_rate); - unsigned long core_rate = max_t(unsigned long, - 500000000, state_rate); + unsigned long core_rate = clamp_t(unsigned long, state_rate, + 500000000, max_clock_rate); drm_dbg(dev, "Raising the core clock at %lu Hz\n", core_rate); @@ -432,14 +436,17 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state) drm_atomic_helper_cleanup_planes(dev, state); if (vc4->is_vc5) { - drm_dbg(dev, "Running the core clock at %lu Hz\n", - new_hvs_state->core_clock_rate); + unsigned long core_rate = min_t(unsigned long, + max_clock_rate, + new_hvs_state->core_clock_rate); + + drm_dbg(dev, "Running the core clock at %lu Hz\n", core_rate); /* * Request a clock rate based on the current HVS * requirements. */ - WARN_ON(clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate)); + WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); drm_dbg(dev, "Core clock actual rate: %lu Hz\n", clk_get_rate(hvs->core_clk)); -- b4 0.10.0-dev-a76f5