From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAACCC282E7 for ; Mon, 15 Aug 2022 12:09:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232111AbiHOMI6 (ORCPT ); Mon, 15 Aug 2022 08:08:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229605AbiHOMIx (ORCPT ); Mon, 15 Aug 2022 08:08:53 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9037726106; Mon, 15 Aug 2022 05:08:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660565332; x=1692101332; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=LYdbdaSxPnkWKQtEEtEDtnmk+PnqxeXBOvUXZFgkiHU=; b=WEgvtiUQ4TpxzXR8kSkPQ01f3bhOGkE6szI8YKnL0pxzmaeyczODfjm5 GtTj09k1BeVIYPqQGLXTZkZRtJlN9YOVL+XSxGFMPNRCYhAyU4uHZSFMT 4MJP6KYy9M/erM2MFEl4ZGWXaJTndUKv+PFKDB6utvAGKaJGyIcqBCIaM VX2sdRr5xmmZKFo4y8Xe9F5F7QUSchBFgYtTo7n1yMmQoiZtOXeC8AK2O wZj/2u239FRyWJytfuQGapdDNOegdFjRzVdMmFheJd2QGbLDEpgqFyiDF IfxTihOKQhA0wdMfiiaBQs1IYGSkc9BljKFECyK01Pz7bWF0WeSkDBiN6 g==; X-IronPort-AV: E=Sophos;i="5.93,238,1654585200"; d="scan'208";a="172452934" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 15 Aug 2022 05:08:51 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 15 Aug 2022 05:08:39 -0700 Received: from dev-powerhorse.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 15 Aug 2022 05:08:37 -0700 From: To: , , , , , , CC: , , Subject: [PATCH v6 0/1] Add Polarfire SoC GPIO support Date: Mon, 15 Aug 2022 13:08:33 +0100 Message-ID: <20220815120834.1562544-1-lewis.hanly@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Lewis Hanly Add a driver to support the Polarfire SoC gpio controller. Tested with latest 5.19 kernel. MPFS gpio interrupts are connected to IOMUX configured by system register GPIO_INTERRUPT_FAB_CR(31:0). Interrupt connection for some GPIO's to the PLIC (Platform Level Interrupt Controller) can be shared (not directly connected) or direct if connection is available. previously upstreamed dt-bindings: gpio: microchip,mpfs-gpio.yaml Changes in v6 Fixed typo causing compile issue with kernel 6.0-rc1 Changes in v5 Added the const for the irqchip, removed in error from v2. Changes in v4 Changed the interrupt handling from Hierarchical flow to chained interrupt flow. The reason for the change was with hierarchical flow we requried a interrupt number mapping array to work with our HW and this was not acceptable. On reviewing the architecture the chained interrupt flow works better for our hardware and configurations which are not fixed in Silicon. Added support to read the optional DT property ngpios. Changes in v3: Changed order in kconfig. Removed blank lines in driver header/source file. Removed BYTE_BOUNDARY variable and use macro to do *4. mpfs_gpio_assign_bit parameter uses macro instead of (i * BYTE_BOUNDARY). Add correct definitions for direction. Change order of variables in mpfs_gpio_irq_set_type function. Return dev_err_probe instead of dev_err. Remove noise of dev_inf. Avoid using of_match_ptr. use devm_gpiochip_add_data(..) Update mpfs_gpio_remove. Changes in v2: Use raw_spinlock. Use __assign_bit() to assign bit, added a bool variable for value. Remove unnecessary checking gpio_index. Remove default from switch statement. Use const for irq_chip, name updated and use mask/unmask. Use latest kernel api irq set_chip. Implemented hierarchical interrupt chip support, although suggested to use chained interrupt flow I believe this fits better. Lewis Hanly (1): gpio: mpfs: add polarfire soc gpio support drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-mpfs.c | 317 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 325 insertions(+) create mode 100644 drivers/gpio/gpio-mpfs.c -- 2.25.1