From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21EBBC25B0E for ; Fri, 19 Aug 2022 09:14:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348027AbiHSJOZ (ORCPT ); Fri, 19 Aug 2022 05:14:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348005AbiHSJOI (ORCPT ); Fri, 19 Aug 2022 05:14:08 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3A463CBEC; Fri, 19 Aug 2022 02:14:05 -0700 (PDT) X-UUID: 08f4bf579be848099ce0c98a3d95d658-20220819 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=lzuHN2o0PHCxOlCMC5PyS2eGduyQugC541Kw8Hzkdso=; b=K73hn0vIol3GnwNvFZnyAp8pNlOXg0dTG25T919vti/sA0dqT4J8vKdX9i5P40SbmBZuJpoE4Tne02FAzXPmXUwAiR/6Z7Gi4dtcGpGwZdinMKLrF5Qa1GgdEBwFQtFkWnFYkHRkiYDBLDr/KPoI5rjp07TRyQkTFl1t/BNgTH8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10,REQID:481fa5bb-835b-44e4-a3f6-00b49bd1ec88,OB:0,L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_ Ham,ACTION:release,TS:0 X-CID-META: VersionHash:84eae18,CLOUDID:f82733c9-6b09-4f60-bf82-12f039f5d530,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:11|1,File: nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 08f4bf579be848099ce0c98a3d95d658-20220819 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1860542636; Fri, 19 Aug 2022 17:13:57 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 19 Aug 2022 17:13:49 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 19 Aug 2022 17:13:49 +0800 From: Chunfeng Yun To: Vinod Koul , Rob Herring CC: Chunfeng Yun , Kishon Vijay Abraham I , Krzysztof Kozlowski , Matthias Brugger , , , , , , Eddie Hung Subject: [PATCH 6/7] phy: phy-mtk-tphy: set utmi 0 register in init() ops Date: Fri, 19 Aug 2022 17:13:43 +0800 Message-ID: <20220819091344.2274-6-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220819091344.2274-1-chunfeng.yun@mediatek.com> References: <20220819091344.2274-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No need repeat to clear utmi 0 register in ->power_on() and ->power_off(), just do it in ->init() Signed-off-by: Chunfeng Yun --- drivers/phy/mediatek/phy-mtk-tphy.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index 79920c066e59..e0f227a0d3cc 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -522,8 +522,8 @@ static void u2_phy_instance_init(struct mtk_tphy *tphy, /* switch to USB function, and enable usb pll */ mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM); - mtk_phy_update_bits(com + U3P_U2PHYDTM0, P2C_RG_XCVRSEL | P2C_RG_DATAIN, - P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0)); + mtk_phy_clear_bits(com + U3P_U2PHYDTM0, + P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_UART_EN); @@ -565,9 +565,6 @@ static void u2_phy_instance_power_on(struct mtk_tphy *tphy, void __iomem *com = u2_banks->com; u32 index = instance->index; - mtk_phy_clear_bits(com + U3P_U2PHYDTM0, - P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); - /* OTG Enable */ mtk_phy_set_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN); @@ -590,8 +587,6 @@ static void u2_phy_instance_power_off(struct mtk_tphy *tphy, void __iomem *com = u2_banks->com; u32 index = instance->index; - mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_RG_XCVRSEL | P2C_RG_DATAIN); - /* OTG Disable */ mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN); -- 2.25.1