From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48995C32772 for ; Fri, 19 Aug 2022 12:28:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348610AbiHSM2L (ORCPT ); Fri, 19 Aug 2022 08:28:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230513AbiHSM2J (ORCPT ); Fri, 19 Aug 2022 08:28:09 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CF4BE3945; Fri, 19 Aug 2022 05:28:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660912088; x=1692448088; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=OuppHraavVdcPp0ARLA7zsvgdMH5yWNmIVqS5fqgRKI=; b=1Mk9Xf4Ast+avbeztI+O2FJqBhx9XNxq5B00trA936Zr+bQYOa8u5SU4 FCK3pg94ER2GY/H0Kjoh5vLxBzmIDw92Ia9LGoJxKIK0C9ZVbJNj/Pooo moYRO6BZ5euUwTM+FBzL/kTq+7slwe6fMGTHgkeaj6x6ZnykxBOSSsF02 o5wNA9ZRA02MC9XHTvtFVK2DJgCLvwJslodVMS5qBnFhrE2cMlUTgeSdB 8ogfoLLVHUX9cMtYkdazJnqa+/2sIyy0+SxsCRo3dQFRQtZsOqGLLfP6B 8U+ub3y+5xAw0j17mLvURUWVGDy3YOjArryGJZGAKkJIO31fUBmbHrZse g==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="173199554" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 05:28:07 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 05:28:02 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 05:27:59 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH 0/6] Add PolarFire SoC Fabric Clock Conditioning Circuitry Support Date: Fri, 19 Aug 2022 13:22:54 +0100 Message-ID: <20220819122259.183600-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hey all, PolarFire SoC has 4 clock source blocks, each with 2 PLLs and 2 DLLs, in the corners of the FPGA fabric. Add bindings, a driver supporting the PLLs and the requisite changes to the devicetrees for PolarFire SoC based boards. These clocks were already in use, but which clock specifically was chosen was decided by the synthesis tool. In our end-of-September release of our FPGA reference design, constraints will be added to force the synthesis tool to pick the "north west" CCC, making it possible to read the configuration from the CCC's registers. I am mainly looking for feedback on the dt-bindings on this version, so that if something dt-abi related needs to change it can be done in advance. There are no maintainers changes in this series, but they are required due to the binding rename. I am waiting for some changes queued in the soc tree before rebasing on a later -rc before including that patch. Thanks, Conor. Conor Dooley (6): dt-bindings: clk: rename mpfs-clkcfg binding dt-bindings: clk: document PolarFire SoC fabric clocks dt-bindings: clk: add PolarFire SoC fabric clock ids clk: microchip: add PolarFire SoC fabric clock support dt-bindings: riscv: microchip: document icicle reference design riscv: dts: microchip: add the mpfs' fabric clock control .../bindings/clock/microchip,mpfs-ccc.yaml | 80 +++++ ...p,mpfs.yaml => microchip,mpfs-clkcfg.yaml} | 2 +- .../devicetree/bindings/riscv/microchip.yaml | 1 + .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 27 +- .../boot/dts/microchip/mpfs-icicle-kit.dts | 4 + .../dts/microchip/mpfs-polarberry-fabric.dtsi | 5 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 34 +- drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/clk-mpfs-ccc.c | 294 ++++++++++++++++++ .../dt-bindings/clock/microchip,mpfs-clock.h | 23 ++ 10 files changed, 458 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml rename Documentation/devicetree/bindings/clock/{microchip,mpfs.yaml => microchip,mpfs-clkcfg.yaml} (96%) create mode 100644 drivers/clk/microchip/clk-mpfs-ccc.c base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868 -- 2.36.1