From: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Michal Simek <michal.simek@xilinx.com>,
Borislav Petkov <bp@alien8.de>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Tony Luck <tony.luck@intel.com>,
James Morse <james.morse@arm.com>,
"Robert Richter" <rric@kernel.org>
Cc: <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-edac@vger.kernel.org>,
<saikrishna12468@gmail.com>, <git@amd.com>,
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>,
Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Subject: [PATCH v3 1/2] dt-bindings: edac: Add bindings for Xilinx ZynqMP OCM
Date: Fri, 26 Aug 2022 13:23:31 +0530 [thread overview]
Message-ID: <20220826075332.30609-2-sai.krishna.potthuri@amd.com> (raw)
In-Reply-To: <20220826075332.30609-1-sai.krishna.potthuri@amd.com>
From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Add bindings for Xilinx ZynqMP OCM controller.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
---
.../xlnx,zynqmp-ocmc-1.0.yaml | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml
new file mode 100644
index 000000000000..ca9fc747bf4f
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynqmp OCM(On-Chip Memory) Controller
+
+maintainers:
+ - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
+ - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
+
+description: |
+ The OCM supports 64-bit wide ECC functionality to detect multi-bit errors
+ and recover from a single-bit memory fault.On a write, if all bytes are
+ being written, the ECC is generated and written into the ECC RAM along with
+ the write-data that is written into the data RAM. If one or more bytes are
+ not written, then the read operation results in an correctable error or
+ uncorrectable error.
+
+properties:
+ compatible:
+ const: xlnx,zynqmp-ocmc-1.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ memory-controller@ff960000 {
+ compatible = "xlnx,zynqmp-ocmc-1.0";
+ reg = <0xff960000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
2.17.1
next prev parent reply other threads:[~2022-08-26 7:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-26 7:53 [PATCH v3 0/2] edac: Add support for Xilinx ZynqMP OCM EDAC Sai Krishna Potthuri
2022-08-26 7:53 ` Sai Krishna Potthuri [this message]
2022-08-26 9:17 ` [PATCH v3 1/2] dt-bindings: edac: Add bindings for Xilinx ZynqMP OCM Krzysztof Kozlowski
2022-08-26 7:53 ` [PATCH v3 2/2] edac: zynqmp_ocm: Add EDAC support for " Sai Krishna Potthuri
2022-08-26 23:32 ` Elliott, Robert (Servers)
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