From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63C9AC38145 for ; Wed, 7 Sep 2022 11:08:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230060AbiIGLIj (ORCPT ); Wed, 7 Sep 2022 07:08:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230009AbiIGLHx (ORCPT ); Wed, 7 Sep 2022 07:07:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34777A3441; Wed, 7 Sep 2022 04:07:51 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9542F618A6; Wed, 7 Sep 2022 11:07:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 11227C4FEB9; Wed, 7 Sep 2022 11:07:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662548869; bh=gug41xRcI/OiU0Kz768lHWGKBf59p8scVt7WnDhxAEE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tpFKflMGympRJ0MouYO9A8Nyca2JWXCiq1eWWsKcIh5Wk8CeNjXf36ZrIafdzhdLo Bgzi/6Q31PBc9Ag5Y6UMT+ZUSUSuv/sWadX0b5h+je1yDo68KTjEGKmFacRXOcyemA wDdyw8PYi8lNOwOkzJiXGS1GgNh5xXltG87WcUn5ZK9NdlxyMzllmiIav9eOsKx8zI lVC9Eo5ybX2imfWxY5UcmtFbK1NjiajyalL5TfXf+f66OXKdWAe+cs/TSUp+2WV+GW urOBn4LSegtCWt8bPzDbRcnvX08F3E/OdfM5r1GlxEz+CQXrukc/DBT916Vyqra/zM XozlOly6kHtsQ== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1oVsuO-0004z9-PF; Wed, 07 Sep 2022 13:07:52 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Kishon Vijay Abraham I , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 08/16] phy: qcom-qmp-ufs: drop unused defines Date: Wed, 7 Sep 2022 13:07:20 +0200 Message-Id: <20220907110728.19092-9-johan+linaro@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220907110728.19092-1-johan+linaro@kernel.org> References: <20220907110728.19092-1-johan+linaro@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Drop defines and enums that are unused since the QMP driver split. Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 34 +------------------------ 1 file changed, 1 insertion(+), 33 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 7bd3c992b841..62e9007137c9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -28,39 +28,15 @@ #define SW_RESET BIT(0) /* QPHY_POWER_DOWN_CONTROL */ #define SW_PWRDN BIT(0) -#define REFCLK_DRV_DSBL BIT(1) /* QPHY_START_CONTROL bits */ #define SERDES_START BIT(0) #define PCS_START BIT(1) -#define PLL_READY_GATE_EN BIT(3) /* QPHY_PCS_STATUS bit */ #define PHYSTATUS BIT(6) -#define PHYSTATUS_4_20 BIT(7) -/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ +/* QPHY_PCS_READY_STATUS bit */ #define PCS_READY BIT(0) -/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ -/* DP PHY soft reset */ -#define SW_DPPHY_RESET BIT(0) -/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ -#define SW_DPPHY_RESET_MUX BIT(1) -/* USB3 PHY soft reset */ -#define SW_USB3PHY_RESET BIT(2) -/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ -#define SW_USB3PHY_RESET_MUX BIT(3) - -/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ -#define USB3_MODE BIT(0) /* enables USB3 mode */ -#define DP_MODE BIT(1) /* enables DP mode */ - -/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ -#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ - #define PHY_INIT_COMPLETE_TIMEOUT 10000 -#define POWER_DOWN_DELAY_US_MIN 10 -#define POWER_DOWN_DELAY_US_MAX 11 - -#define MAX_PROP_NAME 32 /* Define the assumed distance between lanes for underspecified device trees. */ #define QMP_PHY_LEGACY_LANE_STRIDE 0x400 @@ -104,19 +80,11 @@ struct qmp_phy_init_tbl { /* set of registers with offsets different per-PHY */ enum qphy_reg_layout { - /* Common block control registers */ - QPHY_COM_SW_RESET, - QPHY_COM_POWER_DOWN_CONTROL, - QPHY_COM_START_CONTROL, - QPHY_COM_PCS_READY_STATUS, /* PCS registers */ QPHY_SW_RESET, QPHY_START_CTRL, QPHY_PCS_READY_STATUS, - QPHY_PCS_STATUS, QPHY_PCS_POWER_DOWN_CONTROL, - /* PCS_MISC registers */ - QPHY_PCS_MISC_TYPEC_CTRL, /* Keep last to ensure regs_layout arrays are properly initialized */ QPHY_LAYOUT_SIZE }; -- 2.35.1