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From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: linux-kernel@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	stable@vger.kernel.org, Syed Nayyar Waris <syednwaris@gmail.com>,
	Fred Eckert <Frede@cmslaser.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	William Breathitt Gray <william.gray@linaro.org>,
	Sasha Levin <sashal@kernel.org>
Subject: [PATCH 5.19 005/101] counter: 104-quad-8: Implement and utilize register structures
Date: Mon,  3 Oct 2022 09:10:01 +0200	[thread overview]
Message-ID: <20221003070724.637322460@linuxfoundation.org> (raw)
In-Reply-To: <20221003070724.490989164@linuxfoundation.org>

From: William Breathitt Gray <william.gray@linaro.org>

[ Upstream commit daae1ee572d1f99daddef26afe6c6fc7aeea741d ]

Reduce magic numbers and improve code readability by implementing and
utilizing named register data structures.

Link: https://lore.kernel.org/r/20220707171709.36010-1-william.gray@linaro.org/
Cc: Syed Nayyar Waris <syednwaris@gmail.com>
Tested-by: Fred Eckert <Frede@cmslaser.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
Link: https://lore.kernel.org/r/285fdc7c03892251f50bdbf2c28c19998243a6a3.1657813472.git.william.gray@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Stable-dep-of: 2bc54aaa65d2 ("counter: 104-quad-8: Fix skipped IRQ lines during events configuration")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/counter/104-quad-8.c | 166 ++++++++++++++++++++---------------
 1 file changed, 93 insertions(+), 73 deletions(-)

diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c
index 43dde9abfdcf..62c2b7ac4339 100644
--- a/drivers/counter/104-quad-8.c
+++ b/drivers/counter/104-quad-8.c
@@ -33,6 +33,36 @@ MODULE_PARM_DESC(irq, "ACCES 104-QUAD-8 interrupt line numbers");
 
 #define QUAD8_NUM_COUNTERS 8
 
+/**
+ * struct channel_reg - channel register structure
+ * @data:	Count data
+ * @control:	Channel flags and control
+ */
+struct channel_reg {
+	u8 data;
+	u8 control;
+};
+
+/**
+ * struct quad8_reg - device register structure
+ * @channel:		quadrature counter data and control
+ * @interrupt_status:	channel interrupt status
+ * @channel_oper:	enable/reset counters and interrupt functions
+ * @index_interrupt:	enable channel interrupts
+ * @reserved:		reserved for Factory Use
+ * @index_input_levels:	index signal logical input level
+ * @cable_status:	differential encoder cable status
+ */
+struct quad8_reg {
+	struct channel_reg channel[QUAD8_NUM_COUNTERS];
+	u8 interrupt_status;
+	u8 channel_oper;
+	u8 index_interrupt;
+	u8 reserved[3];
+	u8 index_input_levels;
+	u8 cable_status;
+};
+
 /**
  * struct quad8 - device private data structure
  * @lock:		lock to prevent clobbering device states during R/W ops
@@ -48,7 +78,7 @@ MODULE_PARM_DESC(irq, "ACCES 104-QUAD-8 interrupt line numbers");
  * @synchronous_mode:	array of index function synchronous mode configurations
  * @index_polarity:	array of index function polarity configurations
  * @cable_fault_enable:	differential encoder cable status enable configurations
- * @base:		base port address of the device
+ * @reg:		I/O address offset for the device registers
  */
 struct quad8 {
 	spinlock_t lock;
@@ -63,14 +93,9 @@ struct quad8 {
 	unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
 	unsigned int index_polarity[QUAD8_NUM_COUNTERS];
 	unsigned int cable_fault_enable;
-	void __iomem *base;
+	struct quad8_reg __iomem *reg;
 };
 
-#define QUAD8_REG_INTERRUPT_STATUS 0x10
-#define QUAD8_REG_CHAN_OP 0x11
-#define QUAD8_REG_INDEX_INTERRUPT 0x12
-#define QUAD8_REG_INDEX_INPUT_LEVELS 0x16
-#define QUAD8_DIFF_ENCODER_CABLE_STATUS 0x17
 /* Borrow Toggle flip-flop */
 #define QUAD8_FLAG_BT BIT(0)
 /* Carry Toggle flip-flop */
@@ -118,8 +143,7 @@ static int quad8_signal_read(struct counter_device *counter,
 	if (signal->id < 16)
 		return -EINVAL;
 
-	state = ioread8(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) &
-		BIT(signal->id - 16);
+	state = ioread8(&priv->reg->index_input_levels) & BIT(signal->id - 16);
 
 	*level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
 
@@ -130,14 +154,14 @@ static int quad8_count_read(struct counter_device *counter,
 			    struct counter_count *count, u64 *val)
 {
 	struct quad8 *const priv = counter_priv(counter);
-	void __iomem *const base_offset = priv->base + 2 * count->id;
+	struct channel_reg __iomem *const chan = priv->reg->channel + count->id;
 	unsigned int flags;
 	unsigned int borrow;
 	unsigned int carry;
 	unsigned long irqflags;
 	int i;
 
-	flags = ioread8(base_offset + 1);
+	flags = ioread8(&chan->control);
 	borrow = flags & QUAD8_FLAG_BT;
 	carry = !!(flags & QUAD8_FLAG_CT);
 
@@ -148,10 +172,10 @@ static int quad8_count_read(struct counter_device *counter,
 
 	/* Reset Byte Pointer; transfer Counter to Output Latch */
 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
-		 base_offset + 1);
+		 &chan->control);
 
 	for (i = 0; i < 3; i++)
-		*val |= (unsigned long)ioread8(base_offset) << (8 * i);
+		*val |= (unsigned long)ioread8(&chan->data) << (8 * i);
 
 	spin_unlock_irqrestore(&priv->lock, irqflags);
 
@@ -162,7 +186,7 @@ static int quad8_count_write(struct counter_device *counter,
 			     struct counter_count *count, u64 val)
 {
 	struct quad8 *const priv = counter_priv(counter);
-	void __iomem *const base_offset = priv->base + 2 * count->id;
+	struct channel_reg __iomem *const chan = priv->reg->channel + count->id;
 	unsigned long irqflags;
 	int i;
 
@@ -173,27 +197,27 @@ static int quad8_count_write(struct counter_device *counter,
 	spin_lock_irqsave(&priv->lock, irqflags);
 
 	/* Reset Byte Pointer */
-	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
+	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
 
 	/* Counter can only be set via Preset Register */
 	for (i = 0; i < 3; i++)
-		iowrite8(val >> (8 * i), base_offset);
+		iowrite8(val >> (8 * i), &chan->data);
 
 	/* Transfer Preset Register to Counter */
-	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
+	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, &chan->control);
 
 	/* Reset Byte Pointer */
-	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
+	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
 
 	/* Set Preset Register back to original value */
 	val = priv->preset[count->id];
 	for (i = 0; i < 3; i++)
-		iowrite8(val >> (8 * i), base_offset);
+		iowrite8(val >> (8 * i), &chan->data);
 
 	/* Reset Borrow, Carry, Compare, and Sign flags */
-	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
+	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control);
 	/* Reset Error flag */
-	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
+	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control);
 
 	spin_unlock_irqrestore(&priv->lock, irqflags);
 
@@ -246,7 +270,7 @@ static int quad8_function_write(struct counter_device *counter,
 	unsigned int *const quadrature_mode = priv->quadrature_mode + id;
 	unsigned int *const scale = priv->quadrature_scale + id;
 	unsigned int *const synchronous_mode = priv->synchronous_mode + id;
-	void __iomem *const base_offset = priv->base + 2 * id + 1;
+	u8 __iomem *const control = &priv->reg->channel[id].control;
 	unsigned long irqflags;
 	unsigned int mode_cfg;
 	unsigned int idr_cfg;
@@ -266,7 +290,7 @@ static int quad8_function_write(struct counter_device *counter,
 		if (*synchronous_mode) {
 			*synchronous_mode = 0;
 			/* Disable synchronous function mode */
-			iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset);
+			iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
 		}
 	} else {
 		*quadrature_mode = 1;
@@ -292,7 +316,7 @@ static int quad8_function_write(struct counter_device *counter,
 	}
 
 	/* Load mode configuration to Counter Mode Register */
-	iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset);
+	iowrite8(QUAD8_CTR_CMR | mode_cfg, control);
 
 	spin_unlock_irqrestore(&priv->lock, irqflags);
 
@@ -305,7 +329,7 @@ static int quad8_direction_read(struct counter_device *counter,
 {
 	const struct quad8 *const priv = counter_priv(counter);
 	unsigned int ud_flag;
-	void __iomem *const flag_addr = priv->base + 2 * count->id + 1;
+	u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control;
 
 	/* U/D flag: nonzero = up, zero = down */
 	ud_flag = ioread8(flag_addr) & QUAD8_FLAG_UD;
@@ -402,7 +426,6 @@ static int quad8_events_configure(struct counter_device *counter)
 	struct counter_event_node *event_node;
 	unsigned int next_irq_trigger;
 	unsigned long ior_cfg;
-	void __iomem *base_offset;
 
 	spin_lock_irqsave(&priv->lock, irqflags);
 
@@ -437,14 +460,14 @@ static int quad8_events_configure(struct counter_device *counter)
 		ior_cfg = priv->ab_enable[event_node->channel] |
 			  priv->preset_enable[event_node->channel] << 1 |
 			  priv->irq_trigger[event_node->channel] << 3;
-		base_offset = priv->base + 2 * event_node->channel + 1;
-		iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset);
+		iowrite8(QUAD8_CTR_IOR | ior_cfg,
+			 &priv->reg->channel[event_node->channel].control);
 
 		/* Enable IRQ line */
 		irq_enabled |= BIT(event_node->channel);
 	}
 
-	iowrite8(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT);
+	iowrite8(irq_enabled, &priv->reg->index_interrupt);
 
 	spin_unlock_irqrestore(&priv->lock, irqflags);
 
@@ -508,7 +531,7 @@ static int quad8_index_polarity_set(struct counter_device *counter,
 {
 	struct quad8 *const priv = counter_priv(counter);
 	const size_t channel_id = signal->id - 16;
-	void __iomem *const base_offset = priv->base + 2 * channel_id + 1;
+	u8 __iomem *const control = &priv->reg->channel[channel_id].control;
 	unsigned long irqflags;
 	unsigned int idr_cfg = index_polarity << 1;
 
@@ -519,7 +542,7 @@ static int quad8_index_polarity_set(struct counter_device *counter,
 	priv->index_polarity[channel_id] = index_polarity;
 
 	/* Load Index Control configuration to Index Control Register */
-	iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset);
+	iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
 
 	spin_unlock_irqrestore(&priv->lock, irqflags);
 
@@ -549,7 +572,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
 {
 	struct quad8 *const priv = counter_priv(counter);
 	const size_t channel_id = signal->id - 16;
-	void __iomem *const base_offset = priv->base + 2 * channel_id + 1;
+	u8 __iomem *const control = &priv->reg->channel[channel_id].control;
 	unsigned long irqflags;
 	unsigned int idr_cfg = synchronous_mode;
 
@@ -566,7 +589,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
 	priv->synchronous_mode[channel_id] = synchronous_mode;
 
 	/* Load Index Control configuration to Index Control Register */
-	iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset);
+	iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
 
 	spin_unlock_irqrestore(&priv->lock, irqflags);
 
@@ -614,7 +637,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
 	struct quad8 *const priv = counter_priv(counter);
 	unsigned int count_mode;
 	unsigned int mode_cfg;
-	void __iomem *const base_offset = priv->base + 2 * count->id + 1;
+	u8 __iomem *const control = &priv->reg->channel[count->id].control;
 	unsigned long irqflags;
 
 	/* Map Generic Counter count mode to 104-QUAD-8 count mode */
@@ -648,7 +671,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
 		mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3;
 
 	/* Load mode configuration to Counter Mode Register */
-	iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset);
+	iowrite8(QUAD8_CTR_CMR | mode_cfg, control);
 
 	spin_unlock_irqrestore(&priv->lock, irqflags);
 
@@ -669,7 +692,7 @@ static int quad8_count_enable_write(struct counter_device *counter,
 				    struct counter_count *count, u8 enable)
 {
 	struct quad8 *const priv = counter_priv(counter);
-	void __iomem *const base_offset = priv->base + 2 * count->id;
+	u8 __iomem *const control = &priv->reg->channel[count->id].control;
 	unsigned long irqflags;
 	unsigned int ior_cfg;
 
@@ -681,7 +704,7 @@ static int quad8_count_enable_write(struct counter_device *counter,
 		  priv->irq_trigger[count->id] << 3;
 
 	/* Load I/O control configuration */
-	iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
+	iowrite8(QUAD8_CTR_IOR | ior_cfg, control);
 
 	spin_unlock_irqrestore(&priv->lock, irqflags);
 
@@ -697,9 +720,9 @@ static int quad8_error_noise_get(struct counter_device *counter,
 				 struct counter_count *count, u32 *noise_error)
 {
 	const struct quad8 *const priv = counter_priv(counter);
-	void __iomem *const base_offset = priv->base + 2 * count->id + 1;
+	u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control;
 
-	*noise_error = !!(ioread8(base_offset) & QUAD8_FLAG_E);
+	*noise_error = !!(ioread8(flag_addr) & QUAD8_FLAG_E);
 
 	return 0;
 }
@@ -717,17 +740,17 @@ static int quad8_count_preset_read(struct counter_device *counter,
 static void quad8_preset_register_set(struct quad8 *const priv, const int id,
 				      const unsigned int preset)
 {
-	void __iomem *const base_offset = priv->base + 2 * id;
+	struct channel_reg __iomem *const chan = priv->reg->channel + id;
 	int i;
 
 	priv->preset[id] = preset;
 
 	/* Reset Byte Pointer */
-	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
+	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
 
 	/* Set Preset Register */
 	for (i = 0; i < 3; i++)
-		iowrite8(preset >> (8 * i), base_offset);
+		iowrite8(preset >> (8 * i), &chan->data);
 }
 
 static int quad8_count_preset_write(struct counter_device *counter,
@@ -816,7 +839,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter,
 					   u8 preset_enable)
 {
 	struct quad8 *const priv = counter_priv(counter);
-	void __iomem *const base_offset = priv->base + 2 * count->id + 1;
+	u8 __iomem *const control = &priv->reg->channel[count->id].control;
 	unsigned long irqflags;
 	unsigned int ior_cfg;
 
@@ -831,7 +854,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter,
 		  priv->irq_trigger[count->id] << 3;
 
 	/* Load I/O control configuration to Input / Output Control Register */
-	iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset);
+	iowrite8(QUAD8_CTR_IOR | ior_cfg, control);
 
 	spin_unlock_irqrestore(&priv->lock, irqflags);
 
@@ -858,7 +881,7 @@ static int quad8_signal_cable_fault_read(struct counter_device *counter,
 	}
 
 	/* Logic 0 = cable fault */
-	status = ioread8(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
+	status = ioread8(&priv->reg->cable_status);
 
 	spin_unlock_irqrestore(&priv->lock, irqflags);
 
@@ -899,8 +922,7 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter,
 	/* Enable is active low in Differential Encoder Cable Status register */
 	cable_fault_enable = ~priv->cable_fault_enable;
 
-	iowrite8(cable_fault_enable,
-		 priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
+	iowrite8(cable_fault_enable, &priv->reg->cable_status);
 
 	spin_unlock_irqrestore(&priv->lock, irqflags);
 
@@ -924,7 +946,7 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
 {
 	struct quad8 *const priv = counter_priv(counter);
 	const size_t channel_id = signal->id / 2;
-	void __iomem *const base_offset = priv->base + 2 * channel_id;
+	struct channel_reg __iomem *const chan = priv->reg->channel + channel_id;
 	unsigned long irqflags;
 
 	spin_lock_irqsave(&priv->lock, irqflags);
@@ -932,12 +954,12 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
 	priv->fck_prescaler[channel_id] = prescaler;
 
 	/* Reset Byte Pointer */
-	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
+	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
 
 	/* Set filter clock factor */
-	iowrite8(prescaler, base_offset);
+	iowrite8(prescaler, &chan->data);
 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
-		 base_offset + 1);
+		 &chan->control);
 
 	spin_unlock_irqrestore(&priv->lock, irqflags);
 
@@ -1085,12 +1107,11 @@ static irqreturn_t quad8_irq_handler(int irq, void *private)
 {
 	struct counter_device *counter = private;
 	struct quad8 *const priv = counter_priv(counter);
-	void __iomem *const base = priv->base;
 	unsigned long irq_status;
 	unsigned long channel;
 	u8 event;
 
-	irq_status = ioread8(base + QUAD8_REG_INTERRUPT_STATUS);
+	irq_status = ioread8(&priv->reg->interrupt_status);
 	if (!irq_status)
 		return IRQ_NONE;
 
@@ -1119,36 +1140,36 @@ static irqreturn_t quad8_irq_handler(int irq, void *private)
 	}
 
 	/* Clear pending interrupts on device */
-	iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP);
+	iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper);
 
 	return IRQ_HANDLED;
 }
 
-static void quad8_init_counter(void __iomem *const base_offset)
+static void quad8_init_counter(struct channel_reg __iomem *const chan)
 {
 	unsigned long i;
 
 	/* Reset Byte Pointer */
-	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
+	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
 	/* Reset filter clock factor */
-	iowrite8(0, base_offset);
+	iowrite8(0, &chan->data);
 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
-		 base_offset + 1);
+		 &chan->control);
 	/* Reset Byte Pointer */
-	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
+	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
 	/* Reset Preset Register */
 	for (i = 0; i < 3; i++)
-		iowrite8(0x00, base_offset);
+		iowrite8(0x00, &chan->data);
 	/* Reset Borrow, Carry, Compare, and Sign flags */
-	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
+	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control);
 	/* Reset Error flag */
-	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
+	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control);
 	/* Binary encoding; Normal count; non-quadrature mode */
-	iowrite8(QUAD8_CTR_CMR, base_offset + 1);
+	iowrite8(QUAD8_CTR_CMR, &chan->control);
 	/* Disable A and B inputs; preset on index; FLG1 as Carry */
-	iowrite8(QUAD8_CTR_IOR, base_offset + 1);
+	iowrite8(QUAD8_CTR_IOR, &chan->control);
 	/* Disable index function; negative index polarity */
-	iowrite8(QUAD8_CTR_IDR, base_offset + 1);
+	iowrite8(QUAD8_CTR_IDR, &chan->control);
 }
 
 static int quad8_probe(struct device *dev, unsigned int id)
@@ -1169,8 +1190,8 @@ static int quad8_probe(struct device *dev, unsigned int id)
 		return -ENOMEM;
 	priv = counter_priv(counter);
 
-	priv->base = devm_ioport_map(dev, base[id], QUAD8_EXTENT);
-	if (!priv->base)
+	priv->reg = devm_ioport_map(dev, base[id], QUAD8_EXTENT);
+	if (!priv->reg)
 		return -ENOMEM;
 
 	/* Initialize Counter device and driver data */
@@ -1185,17 +1206,16 @@ static int quad8_probe(struct device *dev, unsigned int id)
 	spin_lock_init(&priv->lock);
 
 	/* Reset Index/Interrupt Register */
-	iowrite8(0x00, priv->base + QUAD8_REG_INDEX_INTERRUPT);
+	iowrite8(0x00, &priv->reg->index_interrupt);
 	/* Reset all counters and disable interrupt function */
-	iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, priv->base + QUAD8_REG_CHAN_OP);
+	iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, &priv->reg->channel_oper);
 	/* Set initial configuration for all counters */
 	for (i = 0; i < QUAD8_NUM_COUNTERS; i++)
-		quad8_init_counter(priv->base + 2 * i);
+		quad8_init_counter(priv->reg->channel + i);
 	/* Disable Differential Encoder Cable Status for all channels */
-	iowrite8(0xFF, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
+	iowrite8(0xFF, &priv->reg->cable_status);
 	/* Enable all counters and enable interrupt function */
-	iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC,
-		 priv->base + QUAD8_REG_CHAN_OP);
+	iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper);
 
 	err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler,
 			       IRQF_SHARED, counter->name, counter);
-- 
2.35.1




  parent reply	other threads:[~2022-10-03  7:14 UTC|newest]

Thread overview: 118+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-03  7:09 [PATCH 5.19 000/101] 5.19.13-rc1 review Greg Kroah-Hartman
2022-10-03  7:09 ` [PATCH 5.19 001/101] riscv: make t-head erratas depend on MMU Greg Kroah-Hartman
2022-10-03  7:09 ` [PATCH 5.19 002/101] tools/perf: Fix out of bound access to cpu mask array Greg Kroah-Hartman
2022-10-03  7:09 ` [PATCH 5.19 003/101] perf record: Fix cpu mask bit setting for mixed mmaps Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 004/101] counter: 104-quad-8: Utilize iomap interface Greg Kroah-Hartman
2022-10-03  7:10 ` Greg Kroah-Hartman [this message]
2022-10-03  7:10 ` [PATCH 5.19 006/101] counter: 104-quad-8: Fix skipped IRQ lines during events configuration Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 007/101] uas: add no-uas quirk for Hiksemi usb_disk Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 008/101] usb-storage: Add Hiksemi USB3-FW to IGNORE_UAS Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 009/101] uas: ignore UAS for Thinkplus chips Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 010/101] usb: typec: ucsi: Remove incorrect warning Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 011/101] thunderbolt: Explicitly reset plug events delay back to USB4 spec value Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 012/101] net: usb: qmi_wwan: Add new usb-id for Dell branded EM7455 Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 013/101] Input: snvs_pwrkey - fix SNVS_HPVIDR1 register address Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 014/101] can: c_can: dont cache TX messages for C_CAN cores Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 015/101] clk: ingenic-tcu: Properly enable registers before accessing timers Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 016/101] wifi: mac80211: ensure vif queues are operational after start Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 017/101] x86/sgx: Do not fail on incomplete sanitization on premature stop of ksgxd Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 018/101] frontswap: dont call ->init if no ops are registered Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 019/101] ARM: dts: integrator: Tag PCI host with device_type Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 020/101] ntfs: fix BUG_ON in ntfs_lookup_inode_by_name() Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 021/101] x86/uaccess: avoid check_object_size() in copy_from_user_nmi() Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 022/101] mm/damon/dbgfs: fix memory leak when using debugfs_lookup() Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 023/101] net: mt7531: only do PLL once after the reset Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 024/101] Revert "firmware: arm_scmi: Add clock management to the SCMI power domain" Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 025/101] powerpc/64s/radix: dont need to broadcast IPI for radix pmd collapse flush Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 026/101] drm/i915/gt: Restrict forced preemption to the active context Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 027/101] drm/amdgpu: Add amdgpu suspend-resume code path under SRIOV Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 028/101] vduse: prevent uninitialized memory accesses Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 029/101] libata: add ATA_HORKAGE_NOLPM for Pioneer BDR-207M and BDR-205 Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 030/101] mm: fix BUG splat with kvmalloc + GFP_ATOMIC Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 031/101] mptcp: factor out __mptcp_close() without socket lock Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 032/101] mptcp: fix unreleased socket in accept queue Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 033/101] mmc: moxart: fix 4-bit bus width and remove 8-bit bus width Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 034/101] mmc: hsq: Fix data stomping during mmc recovery Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 035/101] mm: gup: fix the fast GUP race against THP collapse Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 036/101] mm/page_alloc: fix race condition between build_all_zonelists and page allocation Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 037/101] mm: prevent page_frag_alloc() from corrupting the memory Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 038/101] mm/page_isolation: fix isolate_single_pageblock() isolation behavior Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 039/101] mm: fix dereferencing possible ERR_PTR Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 040/101] mm/migrate_device.c: flush TLB while holding PTL Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 041/101] mm/migrate_device.c: add missing flush_cache_page() Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 042/101] mm/migrate_device.c: copy pte dirty bit to page Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 043/101] mm: fix madivse_pageout mishandling on non-LRU page Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 044/101] mm: bring back update_mmu_cache() to finish_fault() Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 045/101] mm/hugetlb: correct demote page offset logic Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 046/101] mm,hwpoison: check mm when killing accessing process Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 047/101] media: dvb_vb2: fix possible out of bound access Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 048/101] media: rkvdec: Disable H.264 error detection Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 049/101] media: mediatek: vcodec: Drop platform_get_resource(IORESOURCE_IRQ) Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 050/101] media: v4l2-compat-ioctl32.c: zero buffer passed to v4l2_compat_get_array_args() Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 051/101] ARM: dts: am33xx: Fix MMCHS0 dma properties Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 052/101] reset: imx7: Fix the iMX8MP PCIe PHY PERST support Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 053/101] ARM: dts: am5748: keep usb4_tm disabled Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 054/101] soc: sunxi: sram: Actually claim SRAM regions Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 055/101] soc: sunxi: sram: Prevent the driver from being unbound Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 056/101] soc: sunxi: sram: Fix probe function ordering issues Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 057/101] soc: sunxi: sram: Fix debugfs info for A64 SRAM C Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 058/101] ASoC: imx-card: Fix refcount issue with of_node_put Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 059/101] clk: microchip: mpfs: fix clk_cfg array bounds violation Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 060/101] clk: microchip: mpfs: make the rtcs ahb clock critical Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 061/101] arm64: dts: qcom: sm8350: fix UFS PHY serdes size Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 062/101] ASoC: tas2770: Reinit regcache on reset Greg Kroah-Hartman
2022-10-03  7:10 ` [PATCH 5.19 063/101] drm/bridge: lt8912b: add vsync hsync Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 064/101] drm/bridge: lt8912b: set hdmi or dvi mode Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 065/101] drm/bridge: lt8912b: fix corrupted image output Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 066/101] net: macb: Fix ZynqMP SGMII non-wakeup source resume failure Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 067/101] Revert "drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time" Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 068/101] Input: melfas_mip4 - fix return value check in mip4_probe() Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 069/101] gpio: mvebu: Fix check for pwm support on non-A8K platforms Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 070/101] perf parse-events: Break out tracepoint and printing Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 071/101] perf print-events: Fix "perf list" can not display the PMU prefix for some hybrid cache events Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 072/101] perf parse-events: Remove "not supported" " Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 073/101] usbnet: Fix memory leak in usbnet_disconnect() Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 074/101] net: sched: act_ct: fix possible refcount leak in tcf_ct_init() Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 075/101] cxgb4: fix missing unlock on ETHOFLD desc collect fail path Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 076/101] net/mlxbf_gige: Fix an IS_ERR() vs NULL bug in mlxbf_gige_mdio_probe Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 077/101] nvme: Fix IOC_PR_CLEAR and IOC_PR_RELEASE ioctls for nvme devices Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 078/101] wifi: cfg80211: fix MCS divisor value Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 079/101] wifi: mac80211: fix regression with non-QoS drivers Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 080/101] wifi: mac80211: fix memory corruption in minstrel_ht_update_rates() Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 081/101] net: stmmac: power up/down serdes in stmmac_open/release Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 082/101] net: phy: Dont WARN for PHY_UP state in mdio_bus_phy_resume() Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 083/101] selftests: Fix the if conditions of in test_extra_filter() Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 084/101] ice: xsk: change batched Tx descriptor cleaning Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 085/101] ice: xsk: drop power of 2 ring size restriction for AF_XDP Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 086/101] vdpa/ifcvf: fix the calculation of queuepair Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 087/101] virtio-blk: Fix WARN_ON_ONCE in virtio_queue_rq() Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 088/101] vdpa/mlx5: Fix MQ to support non power of two num queues Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 089/101] dont use __kernel_write() on kmap_local_page() Greg Kroah-Hartman
2022-10-03  9:09   ` Geert Uytterhoeven
2022-10-04 17:47     ` Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 090/101] clk: imx: imx6sx: remove the SET_RATE_PARENT flag for QSPI clocks Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 091/101] drm/i915/gt: Perf_limit_reasons are only available for Gen11+ Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 092/101] clk: iproc: Do not rely on node name for correct PLL setup Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 093/101] clk: imx93: drop of_match_ptr Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 094/101] net: mscc: ocelot: fix tagged VLAN refusal while under a VLAN-unaware bridge Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 095/101] net: ethernet: mtk_eth_soc: fix mask of RX_DMA_GET_SPORT{,_V2} Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 096/101] perf test: Fix test case 87 ("perf record tests") for hybrid systems Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 097/101] perf tests record: Fail the test if the errs counter is not zero Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 098/101] KVM: x86: Hide IA32_PLATFORM_DCA_CAP[31:0] from the guest Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 099/101] x86/cacheinfo: Add a cpu_llc_shared_mask() UP variant Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 100/101] x86/alternative: Fix race in try_get_desc() Greg Kroah-Hartman
2022-10-03  7:11 ` [PATCH 5.19 101/101] damon/sysfs: fix possible memleak on damon_sysfs_add_target Greg Kroah-Hartman
2022-10-03 17:51 ` [PATCH 5.19 000/101] 5.19.13-rc1 review Guenter Roeck
2022-10-03 18:50 ` Florian Fainelli
2022-10-03 19:02 ` Justin Forbes
2022-10-03 20:39 ` Slade Watkins
2022-10-03 21:28 ` Shuah Khan
2022-10-03 23:24 ` Zan Aziz
2022-10-04  6:06 ` Ron Economos
2022-10-04  6:48 ` Naresh Kamboju
2022-10-05  9:38   ` Feng Tang
2022-10-06  7:45     ` Naresh Kamboju
2022-10-05 10:50   ` Hyeonggon Yoo
2022-10-04  7:27 ` Bagas Sanjaya
2022-10-04 11:47 ` Sudip Mukherjee (Codethink)
2022-10-04 13:40 ` Fenil Jain

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