From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD8E1C433FE for ; Thu, 6 Oct 2022 22:49:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232246AbiJFWt2 (ORCPT ); Thu, 6 Oct 2022 18:49:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231356AbiJFWtZ (ORCPT ); Thu, 6 Oct 2022 18:49:25 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 158BDB8C05 for ; Thu, 6 Oct 2022 15:49:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665096565; x=1696632565; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=aDjej5/rJPN3I3tmGDUpLBewxj0Svrs1hq3whXtgYL0=; b=CaP5U3Gk4B02MevJJCabGVhP0jNb9PQebDUvnWvaTBnDF2pgxXUROPC+ LCDt/38IiqgLXY9jkqSoWQNQAJ6VuqFWDRZ+wpiBmI10b9r0qZgqIoT2U VPR+rTMD4RdczW54IFGPzl4Q+KiBA6zNhygAL8QPU5eexLFLEGfnIERwK 1GPrQjBYkcpfPC7HiY13nzH1C5fqVwWbfa4MPl5R9cAtoudnsltMqSt8t PeyvncEVusPHfzKO7iXFFwgtpznXBCgOXiu8mAAfMyr9zt1yP7BZIag6D 3SCxuzxj0wr4VxZHu7Z63CfBIzOo33Oj17um93cWubjTWUwPQOQGYD42z Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10492"; a="302311490" X-IronPort-AV: E=Sophos;i="5.95,164,1661842800"; d="scan'208";a="302311490" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2022 15:49:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10492"; a="576012245" X-IronPort-AV: E=Sophos;i="5.95,164,1661842800"; d="scan'208";a="576012245" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga003.jf.intel.com with ESMTP; 06 Oct 2022 15:49:23 -0700 Date: Thu, 6 Oct 2022 15:55:53 -0700 From: Ricardo Neri To: Peter Zijlstra Cc: Juri Lelli , Vincent Guittot , Ricardo Neri , "Ravi V. Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, linux-kernel@vger.kernel.org, "Tim C . Chen" Subject: Re: [RFC PATCH 23/23] x86/process: Reset hardware history in context switch Message-ID: <20221006225553.GB1624@ranerica-svr.sc.intel.com> References: <20220909231205.14009-1-ricardo.neri-calderon@linux.intel.com> <20220909231205.14009-24-ricardo.neri-calderon@linux.intel.com> <20221003230758.GA22466@ranerica-svr.sc.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 06, 2022 at 10:35:36AM +0200, Peter Zijlstra wrote: > On Mon, Oct 03, 2022 at 04:07:58PM -0700, Ricardo Neri wrote: > > On Tue, Sep 27, 2022 at 02:52:24PM +0200, Peter Zijlstra wrote: > > > On Fri, Sep 09, 2022 at 04:12:05PM -0700, Ricardo Neri wrote: > > > > > > > +void reset_hardware_history(void) > > > > +{ > > > > + if (!static_cpu_has(X86_FEATURE_HRESET)) > > > > + return; > > > > If I used cpu_feature_enabled(X86_FEATURE_ITD) along with the CONFIG_HFI_ > > THERMAL and its corresponding DISABLE_MASK bit the code below would be > > compiled out. > > Nobody cares about compiled out -- distro's must enable all this. I see. > So > what counts is the code size, and the alternative is smaller. > > > > > + > > > > + asm volatile("mov %0, %%eax;" __ASM_HRESET "\n" : : > > > > + "r" (hardware_history_features) : "%rax"); > > > > +} > > > > > > asm_inline volatile (ALTERNATIVE("", __ASM_HRESET, X86_FEATURE_HRESET) > > > : : "a" (hardware_history_features) : "memory"); > > > > Do you still prefer have implemented as an ALTERNATIVE? > > Yes, look at the generated code. I did compare the sizes of the two options as several NOPs are added at the end. I will take your code. Thanks and BR, Ricardo