From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5637EC433F5 for ; Fri, 7 Oct 2022 09:35:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229916AbiJGJfG (ORCPT ); Fri, 7 Oct 2022 05:35:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229514AbiJGJey (ORCPT ); Fri, 7 Oct 2022 05:34:54 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FB292181D; Fri, 7 Oct 2022 02:34:49 -0700 (PDT) X-UUID: bf66a484aad9405a84c302d60e02301a-20221007 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=LDx7k5RFHyQFyr+eb9E7z51WQb2M4Lzn/qohfNC7QSQ=; b=s7tdGzwRR8iyjwnK0H2tGEU7Ok30ukyMszHDUj/dfHeGe+HFD56eJUPtVBrsKR91whseycbkpf02YdVHBqdOaAl+YUyk2xpGinrEq1yb5l1nlXnR1WLeVIrg9PK3dFmJNpLm6YZJ1ydMXPj5KfS9II5/4TbjRlHOKVZ4WHq1ZI0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:70c34b60-3469-425a-8277-5aea3e3395b7,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.11,REQID:70c34b60-3469-425a-8277-5aea3e3395b7,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:39a5ff1,CLOUDID:3d85d7b8-daef-48a8-8c50-40026d6a74c2,B ulkID:221006200721A1C8BBE7,BulkQuantity:70,Recheck:0,SF:38|28|17|19|48|823 |824,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:41,QS:nil,BEC:nil, COL:0 X-UUID: bf66a484aad9405a84c302d60e02301a-20221007 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1955513913; Fri, 07 Oct 2022 17:34:41 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 7 Oct 2022 17:34:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 7 Oct 2022 17:34:40 +0800 From: Allen-KH Cheng To: Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski , "Matthias Brugger" , Rob Herring , CC: , , , , , , Allen-KH Cheng Subject: [PATCH v2 1/8] arm64: dts: mediatek: mt8186: Fix watchdog compatible Date: Fri, 7 Oct 2022 17:34:30 +0800 Message-ID: <20221007093437.12228-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221007093437.12228-1-allen-kh.cheng@mediatek.com> References: <20221007093437.12228-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: AngeloGioacchino Del Regno MT8186's watchdog embeds a reset controller and needs only the mediatek,mt8186-wdt compatible string as the MT6589 one is there for watchdogs that don't have any reset controller capability. Fixes: 2e78620b1350 ("arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile") Signed-off-by: AngeloGioacchino Del Regno Co-developed-by: Allen-KH Cheng Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 64693c17af9e..e4366144cca5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -330,8 +330,7 @@ }; watchdog: watchdog@10007000 { - compatible = "mediatek,mt8186-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt8186-wdt"; mediatek,disable-extrst; reg = <0 0x10007000 0 0x1000>; #reset-cells = <1>; -- 2.18.0