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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT018.mail.protection.outlook.com (10.13.172.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Sun, 9 Oct 2022 07:11:29 +0000 Received: from pyuan-Cloudripper.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Sun, 9 Oct 2022 02:11:24 -0500 From: Perry Yuan To: , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v2 6/9] cpufreq: amd_pstate: add AMD pstate EPP support for shared memory type processor Date: Sun, 9 Oct 2022 15:10:30 +0800 Message-ID: <20221009071033.21170-7-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221009071033.21170-1-Perry.Yuan@amd.com> References: <20221009071033.21170-1-Perry.Yuan@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT018:EE_|DM4PR12MB5149:EE_ X-MS-Office365-Filtering-Correlation-Id: b16be755-30c9-4a4b-ac41-08daa9c57d08 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2022 07:11:29.6937 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b16be755-30c9-4a4b-ac41-08daa9c57d08 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5149 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Energy Performance Preference support for AMD SOCs which do not contain a designated MSR for CPPC support. A shared memory interface is used for CPPC on these SOCs and the ACPI PCC channel is used to enable EPP and reset the desired performance. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 14a275c22aff..4c24fe391a55 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -135,12 +135,25 @@ static inline int pstate_enable(bool enable) static int cppc_enable(bool enable) { + struct cppc_perf_ctrls perf_ctrls; int cpu, ret = 0; for_each_present_cpu(cpu) { ret = cppc_set_enable(cpu, enable); if (ret) return ret; + if (epp_enabled) { + /* Enable autonomous mode for EPP */ + ret = cppc_set_auto_epp(cpu, enable); + if (ret) + return ret; + + /* Set desired perf as zero to allow EPP firmware control */ + perf_ctrls.desired_perf = 0; + ret = cppc_set_perf(cpu, &perf_ctrls); + if (ret) + return ret; + } } return ret; -- 2.34.1