[PATCH v1 0/3] Add driver nodes for MT8195 SoC

[PATCH v1 0/3] Add driver nodes for MT8195 SoC

[Tinghan Shen]

Add pcie and venc nodes for MT8195 SoC.

This series is based on linux-next/next-20221014.
Depends on https://lore.kernel.org/all/20221001030752.14486-1-irui.wang@mediatek.com/ 

---

Jianjun Wang (1):
  dt-bindings: PCI: mediatek-gen3: Add iommu and power-domain support

Tinghan Shen (2):
  arm64: dts: mt8195: Add pcie and pcie phy nodes
  arm64: dts: mt8195: Add venc node

 .../bindings/pci/mediatek-pcie-gen3.yaml      | 115 ++++++++++++
 arch/arm64/boot/dts/mediatek/mt8195.dtsi      | 167 ++++++++++++++++++
 2 files changed, 282 insertions(+)

-- 
2.18.0

[PATCH v1 1/3] dt-bindings: PCI: mediatek-gen3: Add iommu and power-domain support

[Tinghan Shen]

From: Jianjun Wang <jianjun.wang@mediatek.com>

Add iommu and power-domain support, and add examples for MT8195, which
has two PCIe ports with different clocks and phys.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Signed-off-by: TingHan Shen <tinghan.shen@mediatek.com>
---
 .../bindings/pci/mediatek-pcie-gen3.yaml      | 115 ++++++++++++++++++
 1 file changed, 115 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index c00be39af64e..089074b5fa95 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -70,6 +70,12 @@ properties:
     minItems: 1
     maxItems: 8
 
+  iommu-map:
+    maxItems: 1
+
+  iommu-map-mask:
+    maxItems: 1
+
   resets:
     minItems: 1
     maxItems: 2
@@ -107,6 +113,9 @@ properties:
     items:
       - const: pcie-phy
 
+  power-domains:
+    maxItems: 1
+
   '#interrupt-cells':
     const: 1
 
@@ -191,3 +200,109 @@ examples:
             };
         };
     };
+
+  - |
+    #include <dt-bindings/clock/mt8195-clk.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/memory/mt8195-memory-port.h>
+    #include <dt-bindings/phy/phy.h>
+    #include <dt-bindings/power/mt8195-power.h>
+
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        pcie0: pcie@112f0000 {
+            compatible = "mediatek,mt8195-pcie", "mediatek,mt8192-pcie";
+            device_type = "pci";
+            #address-cells = <3>;
+            #size-cells = <2>;
+            reg = <0x00 0x112f0000 0x00 0x4000>;
+            reg-names = "pcie-mac";
+            interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
+            bus-range = <0x00 0xff>;
+            ranges = <0x81000000 0x00 0x20000000 0x00
+                      0x20000000 0x00 0x200000>,
+                     <0x82000000 0x00 0x20200000 0x00
+                      0x20200000 0x00 0x3e00000>;
+
+            iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
+            iommu-map-mask = <0x0>;
+
+            clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
+                     <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
+                     <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
+                     <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
+                     <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
+                     <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
+            clock-names = "pl_250m", "tl_26m", "tl_96m",
+                          "tl_32k", "peri_26m", "peri_mem";
+            assigned-clocks = <&topckgen CLK_TOP_TL>;
+            assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
+
+            phys = <&pciephy>;
+            phy-names = "pcie-phy";
+
+            power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
+
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 0x7>;
+            interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+                            <0 0 0 2 &pcie_intc0 1>,
+                            <0 0 0 3 &pcie_intc0 2>,
+                            <0 0 0 4 &pcie_intc0 3>;
+            pcie_intc0: interrupt-controller {
+                      #address-cells = <0>;
+                      #interrupt-cells = <1>;
+                      interrupt-controller;
+            };
+        };
+
+        pcie1: pcie@112f8000 {
+            compatible = "mediatek,mt8195-pcie", "mediatek,mt8192-pcie";
+            device_type = "pci";
+            #address-cells = <3>;
+            #size-cells = <2>;
+            reg = <0x00 0x112f8000 0x00 0x4000>;
+            reg-names = "pcie-mac";
+            interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
+            bus-range = <0x00 0xff>;
+            ranges = <0x81000000 0x00 0x24000000 0x00
+                      0x24000000 0x00 0x200000>,
+                     <0x82000000 0x00 0x24200000 0x00
+                      0x24200000 0x00 0x3e00000>;
+
+            iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
+            iommu-map-mask = <0x0>;
+
+            clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
+                     <&clk26m>,
+                     <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
+                     <&clk26m>,
+                     <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
+                     /* Designer has connect pcie1 with peri_mem_p0 clock */
+                     <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
+            clock-names = "pl_250m", "tl_26m", "tl_96m",
+                          "tl_32k", "peri_26m", "peri_mem";
+            assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
+            assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
+
+            phys = <&u3port1 PHY_TYPE_PCIE>;
+            phy-names = "pcie-phy";
+
+            power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
+
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 0x7>;
+            interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+                            <0 0 0 2 &pcie_intc1 1>,
+                            <0 0 0 3 &pcie_intc1 2>,
+                            <0 0 0 4 &pcie_intc1 3>;
+            pcie_intc1: interrupt-controller {
+                      #address-cells = <0>;
+                      #interrupt-cells = <1>;
+                      interrupt-controller;
+            };
+        };
+    };
-- 
2.18.0

[PATCH v1 2/3] arm64: dts: mt8195: Add pcie and pcie phy nodes

[Tinghan Shen]

Add pcie and pcie phy nodes for mt8195.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 143 +++++++++++++++++++++++
 1 file changed, 143 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index d03f0c2b8233..903e92d6156f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1182,6 +1182,104 @@
 			status = "disabled";
 		};
 
+		pcie0: pcie@112f0000 {
+			compatible = "mediatek,mt8195-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x112f0000 0 0x4000>;
+			reg-names = "pcie-mac";
+			interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0 0x20000000
+				  0x0 0x20000000 0 0x200000>,
+				 <0x82000000 0 0x20200000
+				  0x0 0x20200000 0 0x3e00000>;
+
+			iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
+			iommu-map-mask = <0x0>;
+
+			clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
+				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
+				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
+				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
+				 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
+				 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
+			clock-names = "pl_250m", "tl_26m", "tl_96m",
+				      "tl_32k", "peri_26m", "peri_mem";
+			assigned-clocks = <&topckgen CLK_TOP_TL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
+
+			phys = <&pciephy>;
+			phy-names = "pcie-phy";
+
+			power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+					<0 0 0 2 &pcie_intc0 1>,
+					<0 0 0 3 &pcie_intc0 2>,
+					<0 0 0 4 &pcie_intc0 3>;
+			status = "disabled";
+
+			pcie_intc0: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		pcie1: pcie@112f8000 {
+			compatible = "mediatek,mt8195-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x112f8000 0 0x4000>;
+			reg-names = "pcie-mac";
+			interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0 0x24000000
+				  0x0 0x24000000 0 0x200000>,
+				 <0x82000000 0 0x24200000
+				  0x0 0x24200000 0 0x3e00000>;
+
+			iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
+			iommu-map-mask = <0x0>;
+
+			clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
+				 <&clk26m>,
+				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
+				 <&clk26m>,
+				 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
+				 /* Designer has connect pcie1 with peri_mem_p0 clock */
+				 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
+			clock-names = "pl_250m", "tl_26m", "tl_96m",
+				      "tl_32k", "peri_26m", "peri_mem";
+			assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
+			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
+
+			phys = <&u3port1 PHY_TYPE_PCIE>;
+			phy-names = "pcie-phy";
+			power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+					<0 0 0 2 &pcie_intc1 1>,
+					<0 0 0 3 &pcie_intc1 2>,
+					<0 0 0 4 &pcie_intc1 3>;
+			status = "disabled";
+
+			pcie_intc1: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
 		nor_flash: spi@1132c000 {
 			compatible = "mediatek,mt8195-nor",
 				     "mediatek,mt8173-nor";
@@ -1241,6 +1339,34 @@
 				reg = <0x189 0x2>;
 				bits = <7 5>;
 			};
+			pciephy_rx_ln1: pciephy-rx-ln1@190 {
+				reg = <0x190 0x1>;
+				bits = <0 4>;
+			};
+			pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190 {
+				reg = <0x190 0x1>;
+				bits = <4 4>;
+			};
+			pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191 {
+				reg = <0x191 0x1>;
+				bits = <0 4>;
+			};
+			pciephy_rx_ln0: pciephy-rx-ln0@191 {
+				reg = <0x191 0x1>;
+				bits = <4 4>;
+			};
+			pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192 {
+				reg = <0x192 0x1>;
+				bits = <0 4>;
+			};
+			pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192 {
+				reg = <0x192 0x1>;
+				bits = <4 4>;
+			};
+			pciephy_glb_intr: pciephy-glb-intr@193 {
+				reg = <0x193 0x1>;
+				bits = <0 4>;
+			};
 		};
 
 		u3phy2: t-phy@11c40000 {
@@ -1461,6 +1587,23 @@
 			};
 		};
 
+		pciephy: phy@11e80000 {
+			compatible = "mediatek,mt8195-pcie-phy";
+			reg = <0 0x11e80000 0 0x10000>;
+			reg-names = "sif";
+			nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
+				      <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>,
+				      <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>,
+				      <&pciephy_rx_ln1>;
+			nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
+					   "tx_ln0_nmos", "rx_ln0",
+					   "tx_ln1_pmos", "tx_ln1_nmos",
+					   "rx_ln1";
+			power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		ufsphy: ufs-phy@11fa0000 {
 			compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
 			reg = <0 0x11fa0000 0 0xc000>;
-- 
2.18.0

[PATCH v1 3/3] arm64: dts: mt8195: Add venc node

[Tinghan Shen]

Add venc node for mt8195 SoC.

Signed-off-by: Irui Wang <irui.wang@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 903e92d6156f..7cf2f7ef4ec6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2163,6 +2163,30 @@
 			power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
 		};
 
+		venc: venc@1a020000 {
+			compatible = "mediatek,mt8195-vcodec-enc";
+			reg = <0 0x1a020000 0 0x10000>;
+			iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
+				 <&iommu_vdo M4U_PORT_L19_VENC_REC>,
+				 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
+				 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
+				 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
+				 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
+				 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
+				 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
+				 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
+			interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
+			mediatek,scp = <&scp>;
+			clocks = <&vencsys CLK_VENC_VENC>;
+			clock-names = "venc_sel";
+			assigned-clocks = <&topckgen CLK_TOP_VENC>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+		};
+
 		vencsys_core1: clock-controller@1b000000 {
 			compatible = "mediatek,mt8195-vencsys_core1";
 			reg = <0 0x1b000000 0 0x1000>;
-- 
2.18.0

Re: [PATCH v1 1/3] dt-bindings: PCI: mediatek-gen3: Add iommu and power-domain support

[Rob Herring]

On Mon, Oct 17, 2022 at 03:08:56PM +0800, Tinghan Shen wrote:
> From: Jianjun Wang <jianjun.wang@mediatek.com>
> 
> Add iommu and power-domain support, and add examples for MT8195, which
> has two PCIe ports with different clocks and phys.

Is that really a big enough difference to add a whole other example 
when we have a dts file with it too? I don't think so, and we certainly 
don't need to show all instances either.

Rob

Re: [PATCH v1 1/3] dt-bindings: PCI: mediatek-gen3: Add iommu and power-domain support

[TingHan Shen (沈廷翰)]

Hi Rob,

On Mon, 2022-10-17 at 13:42 -0500, Rob Herring wrote:
> On Mon, Oct 17, 2022 at 03:08:56PM +0800, Tinghan Shen wrote:
> > From: Jianjun Wang <jianjun.wang@mediatek.com>
> > 
> > Add iommu and power-domain support, and add examples for MT8195, which
> > has two PCIe ports with different clocks and phys.
> 
> Is that really a big enough difference to add a whole other example 
> when we have a dts file with it too? I don't think so, and we certainly 
> don't need to show all instances either.
> 
> Rob

Ok, I'll remove the example at next version.
Thank you.


Best regards,
TingHan

Re: [PATCH v1 3/3] arm64: dts: mt8195: Add venc node

[Krzysztof Kozlowski]

On 17/10/2022 03:08, Tinghan Shen wrote:
> Add venc node for mt8195 SoC.
> 
> Signed-off-by: Irui Wang <irui.wang@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 903e92d6156f..7cf2f7ef4ec6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -2163,6 +2163,30 @@
>  			power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
>  		};
>  
> +		venc: venc@1a020000 {

I think you called this video-codec in other patches... Would be great
if you (you as folks working on Mediatek from Mediatek) keep patches
consistent...


> +			compatible = "mediatek,mt8195-vcodec-enc";
> +			reg = <0 0x1a020000 0 0x10000>;


Best regards,
Krzysztof

Re: [PATCH v1 3/3] arm64: dts: mt8195: Add venc node

[AngeloGioacchino Del Regno]

Il 17/10/22 09:08, Tinghan Shen ha scritto:
> Add venc node for mt8195 SoC.
> 
> Signed-off-by: Irui Wang <irui.wang@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 903e92d6156f..7cf2f7ef4ec6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -2163,6 +2163,30 @@
>   			power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
>   		};
>   
> +		venc: venc@1a020000 {

As Krzysztof also said, this is video-codec@1a020000.

Also, there's one more thing... MT8195 has two video encoder cores, but this
node is only for the first one. There's a second instance at 0x1b020000: please
add it.

Regards,
Angelo

Re: [PATCH v1 2/3] arm64: dts: mt8195: Add pcie and pcie phy nodes

[AngeloGioacchino Del Regno]

Il 17/10/22 09:08, Tinghan Shen ha scritto:
> Add pcie and pcie phy nodes for mt8195.
> 
> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 143 +++++++++++++++++++++++
>   1 file changed, 143 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index d03f0c2b8233..903e92d6156f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1182,6 +1182,104 @@
>   			status = "disabled";
>   		};
>   
> +		pcie0: pcie@112f0000 {
> +			compatible = "mediatek,mt8195-pcie",
> +				     "mediatek,mt8192-pcie";

..snip..

> +
> +			phys = <&pciephy>;
> +			phy-names = "pcie-phy";
> +
> +			power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;

You're missing the resets:

			resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
			reset-names = "mac";

> +
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 7>;

..snip..

> +		};
> +
> +		pcie1: pcie@112f8000 {
> +			compatible = "mediatek,mt8195-pcie",
> +				     "mediatek,mt8192-pcie";

..snip..

> +			power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;

Here too:
			resets = <&infracfg_ao MT8195_INFRA_RST2_USBSIF_P1_SWRST>,
				 <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
			reset-names = "phy", "mac";

> +
> +			#interrupt-cells = <1>;

..snip..

> @@ -1241,6 +1339,34 @@
>   				reg = <0x189 0x2>;
>   				bits = <7 5>;
>   			};
> +			pciephy_rx_ln1: pciephy-rx-ln1@190 {
> +				reg = <0x190 0x1>;
> +				bits = <0 4>;
> +			};
> +			pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190 {

Please run dtbs_check and try to build the kernel before pushing commits upstream.
This will give you a not-so-nice warning and that shall not happen.

You can solve it by naming these nodes like:
pciephy-rx-ln1@190,1
pciephy-tx-ln1-nmos@190,2

...etc

Regards,
Angelo

Re: [PATCH v1 3/3] arm64: dts: mt8195: Add venc node

[Irui Wang]

On Wed, 2022-10-19 at 10:51 +0200, AngeloGioacchino Del Regno wrote:
> Il 17/10/22 09:08, Tinghan Shen ha scritto:
> > Add venc node for mt8195 SoC.
> > 
> > Signed-off-by: Irui Wang <irui.wang@mediatek.com>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24
> > ++++++++++++++++++++++++
> >   1 file changed, 24 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 903e92d6156f..7cf2f7ef4ec6 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -2163,6 +2163,30 @@
> >   			power-domains = <&spm
> > MT8195_POWER_DOMAIN_VENC>;
> >   		};
> >   
> > +		venc: venc@1a020000 {
> 
> As Krzysztof also said, this is video-codec@1a020000.
> 
> Also, there's one more thing... MT8195 has two video encoder cores,
> but this
> node is only for the first one. There's a second instance at
> 0x1b020000: please
> add it.
Dear Angelo,

The second video encoder core 0x1b020000 is not ready in driver, there
is only one core 0x1a020000 used, so we don't need add it in current
patch now.

Thanks
Best Regards
> 
> Regards,
> Angelo
> 

Re: [PATCH v1 2/3] arm64: dts: mt8195: Add pcie and pcie phy nodes

[Jianjun Wang]

Hi Angelo,

Thanks for your review.

On Wed, 2022-10-19 at 10:55 +0200, AngeloGioacchino Del Regno wrote:
> Il 17/10/22 09:08, Tinghan Shen ha scritto:
> > Add pcie and pcie phy nodes for mt8195.
> > 
> > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 143
> > +++++++++++++++++++++++
> >   1 file changed, 143 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index d03f0c2b8233..903e92d6156f 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1182,6 +1182,104 @@
> >   			status = "disabled";
> >   		};
> >   
> > +		pcie0: pcie@112f0000 {
> > +			compatible = "mediatek,mt8195-pcie",
> > +				     "mediatek,mt8192-pcie";
> 
> ..snip..
> 
> > +
> > +			phys = <&pciephy>;
> > +			phy-names = "pcie-phy";
> > +
> > +			power-domains = <&spm
> > MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
> 
> You're missing the resets:
> 
> 			resets = <&infracfg_ao
> MT8195_INFRA_RST2_PCIE_P0_SWRST>;
> 			reset-names = "mac";
> 
> > +
> > +			#interrupt-cells = <1>;
> > +			interrupt-map-mask = <0 0 0 7>;
> 
> ..snip..
> 
> > +		};
> > +
> > +		pcie1: pcie@112f8000 {
> > +			compatible = "mediatek,mt8195-pcie",
> > +				     "mediatek,mt8192-pcie";
> 
> ..snip..
> 
> > +			power-domains = <&spm
> > MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
> 
> Here too:
> 			resets = <&infracfg_ao
> MT8195_INFRA_RST2_USBSIF_P1_SWRST>,

Reset the combo-phy in PCIe driver will cause side effect on USB2 port,
so this reset cannot be added.

We will fix others in the next version.

Thanks.
> 				 <&infracfg_ao
> MT8195_INFRA_RST2_PCIE_P1_SWRST>;
> 			reset-names = "phy", "mac";
> 
> > +
> > +			#interrupt-cells = <1>;
> 
> ..snip..
> 
> > @@ -1241,6 +1339,34 @@
> >   				reg = <0x189 0x2>;
> >   				bits = <7 5>;
> >   			};
> > +			pciephy_rx_ln1: pciephy-rx-ln1@190 {
> > +				reg = <0x190 0x1>;
> > +				bits = <0 4>;
> > +			};
> > +			pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190 {
> 
> Please run dtbs_check and try to build the kernel before pushing
> commits upstream.
> This will give you a not-so-nice warning and that shall not happen.
> 
> You can solve it by naming these nodes like:
> pciephy-rx-ln1@190,1
> pciephy-tx-ln1-nmos@190,2
> 
> ...etc
> 
> Regards,
> Angelo
> 
>