From: Patrick Delaunay <patrick.delaunay@foss.st.com>
To: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>
Subject: [PATCH v2 1/3] nvmem: stm32: move STM32MP15_BSEC_NUM_LOWER in config
Date: Mon, 17 Oct 2022 17:49:55 +0200 [thread overview]
Message-ID: <20221017174953.v2.1.I95e71328dd654723bd4c57206bd008ff81c726bb@changeid> (raw)
In-Reply-To: <20221017154957.277120-1-patrick.delaunay@foss.st.com>
Support STM32MP15_BSEC_NUM_LOWER in stm32 romem config to prepare
the next SoC in STM32MP family.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---
Changes in v2:
- Add patch "move STM32MP15_BSEC_NUM_LOWER in config" in the serie,
solve dependency issue for "priv->lower" in patch "nvmem: stm32:
add warning when upper OTPs are updated"
drivers/nvmem/stm32-romem.c | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/nvmem/stm32-romem.c b/drivers/nvmem/stm32-romem.c
index 354be526897f..d93baee01d7b 100644
--- a/drivers/nvmem/stm32-romem.c
+++ b/drivers/nvmem/stm32-romem.c
@@ -22,16 +22,15 @@
/* shadow registers offest */
#define STM32MP15_BSEC_DATA0 0x200
-/* 32 (x 32-bits) lower shadow registers */
-#define STM32MP15_BSEC_NUM_LOWER 32
-
struct stm32_romem_cfg {
int size;
+ u8 lower;
};
struct stm32_romem_priv {
void __iomem *base;
struct nvmem_config cfg;
+ u8 lower;
};
static int stm32_romem_read(void *context, unsigned int offset, void *buf,
@@ -85,7 +84,7 @@ static int stm32_bsec_read(void *context, unsigned int offset, void *buf,
for (i = roffset; (i < roffset + rbytes); i += 4) {
u32 otp = i >> 2;
- if (otp < STM32MP15_BSEC_NUM_LOWER) {
+ if (otp < priv->lower) {
/* read lower data from shadow registers */
val = readl_relaxed(
priv->base + STM32MP15_BSEC_DATA0 + i);
@@ -159,6 +158,8 @@ static int stm32_romem_probe(struct platform_device *pdev)
priv->cfg.priv = priv;
priv->cfg.owner = THIS_MODULE;
+ priv->lower = 0;
+
cfg = (const struct stm32_romem_cfg *)
of_match_device(dev->driver->of_match_table, dev)->data;
if (!cfg) {
@@ -167,6 +168,7 @@ static int stm32_romem_probe(struct platform_device *pdev)
priv->cfg.reg_read = stm32_romem_read;
} else {
priv->cfg.size = cfg->size;
+ priv->lower = cfg->lower;
priv->cfg.reg_read = stm32_bsec_read;
priv->cfg.reg_write = stm32_bsec_write;
}
@@ -174,8 +176,17 @@ static int stm32_romem_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg));
}
+/*
+ * STM32MP15 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)
+ * => 96 x 32-bits data words
+ * - Lower: 1K bits, 2:1 redundancy, incremental bit programming
+ * => 32 (x 32-bits) lower shadow registers = words 0 to 31
+ * - Upper: 2K bits, ECC protection, word programming only
+ * => 64 (x 32-bits) = words 32 to 95
+ */
static const struct stm32_romem_cfg stm32mp15_bsec_cfg = {
- .size = 384, /* 96 x 32-bits data words */
+ .size = 384,
+ .lower = 32,
};
static const struct of_device_id stm32_romem_of_match[] = {
--
2.25.1
next prev parent reply other threads:[~2022-10-17 15:50 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-17 15:49 [PATCH v2 0/3] nvmem: stm32: several minor improvements Patrick Delaunay
2022-10-17 15:49 ` Patrick Delaunay [this message]
2022-10-17 15:49 ` [PATCH v2 2/3] nvmem: stm32: add warning when upper OTPs are updated Patrick Delaunay
2022-10-17 15:49 ` [PATCH v2 3/3] nvmem: stm32: add nvmem type attribute Patrick Delaunay
2022-10-31 17:41 ` [PATCH v2 0/3] nvmem: stm32: several minor improvements Srinivas Kandagatla
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