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Thu, 20 Oct 2022 01:33:45 -0700 From: Akhil R To: , , , , , , , , , , , CC: Subject: [PATCH RESEND v2 1/3] dt-bindings: dmaengine: Add dma-channel-mask to Tegra GPCDMA Date: Thu, 20 Oct 2022 14:03:20 +0530 Message-ID: <20221020083322.36431-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221020083322.36431-1-akhilrajeev@nvidia.com> References: <20221020083322.36431-1-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT088:EE_|CY5PR12MB6348:EE_ X-MS-Office365-Filtering-Correlation-Id: a693e34f-cc4d-40c3-5816-08dab275d718 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: B74K/VoAkzLrYYbhqFChvXotw/zVnab3S2uiVAWkWXKdlC/ucBvlpswasXWQJPDSGlvHUCItwLNFebPlv4Okk1mYbOXRrE3Cf1AvuPr380lzBKU7MX9Kl4f6ak0//F5/wkPqWNrM7sGDz8A9TRC3C4RXDIFXkoU3yF0L2Rx7ErGQ9lCizL1WNxsLtIQGmjhtvMR9OLiKB+wI5JDefCMUeFwpAUuIDlatV3CcckLkZKF6T8ikJHMYLlzVdOSFxAS76esUsrBhyNpAxOfsZXJOQimmLM9po7tAumJxICm7IjzmqxJAta7gucBZEMHfpH0jHVDUILQlMAUq+ZxLZ5fTFJ1puH1MM1nq3M1hUdAiwzQTlcWqgXqvd8zDO9kqS4w3MIww7vyQTeh7WA9tvJXyVO7U7/0k3Ab7T6Otmqoef4FMHCKAok789xQWV3U5iep9uscLCrGOkSy6vdJLQ1IpeKs1vrgAMHIq2gdu4I8tarxlRhoR7suRkimnrNPsPmLngus8Nh2ckP9Tlc96RaoUf6jWe6wGVwd66ZXVbnZaF87OAoTWdH46E6SC7R60WC8kWrHwXXxIf1WBy4rtxZvXDfghG43if6zxkyI05yF+zcmRmZTpGJ9FJMMkagBGK+P0frLxScUHQjMXDEDTT8ytvZtzceJmYPkuaqGK7DQyJ9jQfJ1BY5ktAlGaGDifazhDducovZ1C/QGn6j6BBcWgUBZ9mRYBlUkovXaDQgTkAVKYCgWS2P/8WpyIOWarRfuqwbwAgOLbeGuBPxdFifcsVoMKGL/ntNme8zVJXB5f5h0= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(396003)(136003)(376002)(451199015)(36840700001)(46966006)(40470700004)(110136005)(8676002)(336012)(70206006)(4326008)(107886003)(70586007)(6666004)(316002)(186003)(2616005)(1076003)(36756003)(86362001)(83380400001)(426003)(40480700001)(2906002)(47076005)(36860700001)(41300700001)(5660300002)(7696005)(26005)(40460700003)(7416002)(8936002)(356005)(478600001)(7636003)(82740400003)(921005)(82310400005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Oct 2022 08:34:01.4086 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a693e34f-cc4d-40c3-5816-08dab275d718 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT088.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6348 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add dma-channel-mask property in Tegra GPCDMA document. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. Now since we can list all 32 channels, update the interrupts property as well to list all 32 interrupts. Signed-off-by: Akhil R Acked-by: Thierry Reding --- .../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml index c8894476b6ab..851bd50ee67f 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -39,7 +39,7 @@ properties: Should contain all of the per-channel DMA interrupts in ascending order with respect to the DMA channel index. minItems: 1 - maxItems: 31 + maxItems: 32 resets: maxItems: 1 @@ -52,6 +52,9 @@ properties: dma-coherent: true + dma-channel-mask: + maxItems: 1 + required: - compatible - reg @@ -60,6 +63,7 @@ required: - reset-names - "#dma-cells" - iommus + - dma-channel-mask additionalProperties: false @@ -108,5 +112,6 @@ examples: #dma-cells = <1>; iommus = <&smmu TEGRA186_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask = <0xfffffffe>; }; ... -- 2.17.1