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Thu, 20 Oct 2022 01:33:53 -0700 From: Akhil R To: , , , , , , , , , , , CC: Subject: [PATCH RESEND v2 2/3] arm64: tegra: Add dma-channel-mask in GPCDMA node Date: Thu, 20 Oct 2022 14:03:21 +0530 Message-ID: <20221020083322.36431-3-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221020083322.36431-1-akhilrajeev@nvidia.com> References: <20221020083322.36431-1-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT032:EE_|CH3PR12MB7500:EE_ X-MS-Office365-Filtering-Correlation-Id: df049db7-560a-4926-7397-08dab275da4d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: XCIxq7JTsCq58aNL7ZiYaBc6dEy4ncI2jHJjF0SJFt1TWGV8oWCavRy3QqUs0FlmK7iU+S1LVLCLOynDbtr8uwtGyCRcrohtzo7fh+2REzXN6x9gmJ7eKOJkpd5kWRu4cRqPRh7tD4g9P1WgvRFwBD1BOGFi8UbDwfIB9Vsw/kfsOrRUpX7Oni1FV8M96KleiTL5EOBzxtVa+umWkzbpb1o77WiGb/y/twybRJNcEnoBhoWdhx8QzAJ7TDyw1uF0K9takkPTjK9y9dOmUBgldSl0FFrGYU16lhlZXi57C31oBC7EUyq7IY6b1D0GarLF8QnPqFOzDfpNDqM215sI2eN7f1qx3fG1/4Qj9pt8fcdcLDTJO//odIvidrz2Lf2XM+xzHkBBb/73Ec4yvzVpTj03EX3G33Im6iUMxGaXr31CXtZgRy+T+iW8/d3gYb2FUDZ4OQF0Hp3QZ0khB9kFBHHyH9DnCwWA4A1H+jhnePi6Xdzynj5bPXJ8cq/w4jfwCMBLqeHablPxF6a4TvYj46uD079c+BsB1tQHXon8n0TMPI7XGLZO8pgFcwCxpkXYxilgtXwkoGBsJQWqrtMZRfOxZBy/IZP0wxqHHkkKJwmbE/WFdD4uFKPJk6U7KCDqQkRP6fKev6rBLo8nsnhowB4TioXltw6HMKL2kiJh/YAsl2zZdihqvhInCU6s1+VSQyrR2+TnqiijjPoiZvETyULXn3mD1Q6rxp/5WR3KP25yKA1fCvnbSJFYSM98c/7KZ3mYxUnquDZtqRX6JDDxXV5qCgQcGlJMtYF/tSxnjTk= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(346002)(376002)(39860400002)(396003)(136003)(451199015)(46966006)(40470700004)(36840700001)(921005)(107886003)(6666004)(8936002)(4326008)(478600001)(70586007)(70206006)(8676002)(110136005)(36756003)(36860700001)(41300700001)(7696005)(426003)(40480700001)(40460700003)(186003)(1076003)(82310400005)(26005)(2616005)(86362001)(336012)(356005)(83380400001)(82740400003)(7636003)(47076005)(316002)(2906002)(7416002)(5660300002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Oct 2022 08:34:06.8210 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df049db7-560a-4926-7397-08dab275da4d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7500 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add dma-channel-mask property in Tegra GPCDMA device tree node. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. Now since we can list all 32 channels, update the interrupts property as well to list all 32 interrupts. Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 6602fe421ee8..db479064ff72 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -78,7 +78,8 @@ reg = <0x0 0x2600000 0x0 0x210000>; resets = <&bpmp TEGRA186_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = , + interrupts = , + , , , , @@ -112,6 +113,7 @@ #dma-cells = <1>; iommus = <&smmu TEGRA186_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask = <0xfffffffe>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 41f3a7e188d0..b009f8145016 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -142,7 +142,8 @@ reg = <0x2600000 0x210000>; resets = <&bpmp TEGRA194_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = , + interrupts = , + , , , , @@ -176,6 +177,7 @@ #dma-cells = <1>; iommus = <&smmu TEGRA194_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask = <0xfffffffe>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 0170bfa8a467..ccc1a4bd094d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -27,7 +27,8 @@ reg = <0x2600000 0x210000>; resets = <&bpmp TEGRA234_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = , + interrupts = , + , , , , @@ -60,6 +61,7 @@ ; #dma-cells = <1>; iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-channel-mask = <0xfffffffe>; dma-coherent; }; -- 2.17.1