From: Kim Phillips <kim.phillips@amd.com>
To: <x86@kernel.org>
Cc: Kim Phillips <kim.phillips@amd.com>,
Borislav Petkov <bp@alien8.de>,
"Boris Ostrovsky" <boris.ostrovsky@oracle.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>, Ingo Molnar <mingo@redhat.com>,
Joao Martins <joao.m.martins@oracle.com>,
Jonathan Corbet <corbet@lwn.net>,
Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Thomas Gleixner <tglx@linutronix.de>,
David Woodhouse <dwmw@amazon.co.uk>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Juergen Gross <jgross@suse.com>,
Peter Zijlstra <peterz@infradead.org>,
Tony Luck <tony.luck@intel.com>, Babu Moger <Babu.Moger@amd.com>,
Tom Lendacky <thomas.lendacky@amd.com>, <kvm@vger.kernel.org>,
<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 3/3] x86/speculation: Support Automatic IBRS under virtualization
Date: Fri, 4 Nov 2022 16:36:51 -0500 [thread overview]
Message-ID: <20221104213651.141057-4-kim.phillips@amd.com> (raw)
In-Reply-To: <20221104213651.141057-1-kim.phillips@amd.com>
VM Guests may want to use Auto IBRS, so propagate the CPUID to them.
Co-developed-by: Babu Moger <Babu.Moger@amd.com>
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
---
arch/x86/kvm/cpuid.c | 5 ++++-
arch/x86/kvm/reverse_cpuid.h | 1 +
arch/x86/kvm/svm/svm.c | 3 +++
arch/x86/kvm/x86.c | 3 +++
4 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 7065462378e2..2524cd82627b 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -730,6 +730,8 @@ void kvm_set_cpu_caps(void)
0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
F(SME_COHERENT));
+ kvm_cpu_cap_mask(CPUID_8000_0021_EAX, F(AUTOIBRS));
+
kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
@@ -1211,12 +1213,13 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
* EAX 0 NNDBP, Processor ignores nested data breakpoints
* EAX 2 LAS, LFENCE always serializing
* EAX 6 NSCB, Null selector clear base
+ * EAX 8 Automatic IBRS
*
* Other defined bits are for MSRs that KVM does not expose:
* EAX 3 SPCL, SMM page configuration lock
* EAX 13 PCMSR, Prefetch control MSR
*/
- entry->eax &= BIT(0) | BIT(2) | BIT(6);
+ entry->eax &= BIT(0) | BIT(2) | BIT(6) | BIT(8);
if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
entry->eax |= BIT(2);
if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h
index a19d473d0184..7eeade35a425 100644
--- a/arch/x86/kvm/reverse_cpuid.h
+++ b/arch/x86/kvm/reverse_cpuid.h
@@ -48,6 +48,7 @@ static const struct cpuid_reg reverse_cpuid[] = {
[CPUID_7_1_EAX] = { 7, 1, CPUID_EAX},
[CPUID_12_EAX] = {0x00000012, 0, CPUID_EAX},
[CPUID_8000_001F_EAX] = {0x8000001f, 0, CPUID_EAX},
+ [CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX},
};
/*
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 58f0077d9357..2add5eb3303f 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -4993,6 +4993,9 @@ static __init int svm_hardware_setup(void)
tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
+ if (boot_cpu_has(X86_FEATURE_AUTOIBRS))
+ kvm_enable_efer_bits(EFER_AUTOIBRS);
+
/* Check for pause filtering support */
if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
pause_filter_count = 0;
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 9cf1ba865562..3dbeda353853 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1687,6 +1687,9 @@ static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
{
+ if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS))
+ return false;
+
if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
return false;
--
2.34.1
next prev parent reply other threads:[~2022-11-04 21:38 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-04 21:36 [PATCH 0/3] x86/speculation: Support Automatic IBRS Kim Phillips
2022-11-04 21:36 ` [PATCH 1/3] x86/cpufeatures: Add support for cpuid leaf 80000021/EAX (FeatureExt2Eax) Kim Phillips
2022-11-04 21:48 ` Borislav Petkov
2022-11-15 23:10 ` Kim Phillips
2022-11-16 11:59 ` Borislav Petkov
2022-11-16 20:22 ` Sean Christopherson
2022-11-16 21:01 ` Borislav Petkov
2022-11-04 21:36 ` [PATCH 2/3] x86/speculation: Support Automatic IBRS Kim Phillips
2022-11-04 21:52 ` Borislav Petkov
2022-11-05 11:10 ` Peter Zijlstra
2022-11-07 22:39 ` Kim Phillips
2022-11-07 23:41 ` Dave Hansen
2022-11-08 8:06 ` Peter Zijlstra
2022-11-11 12:09 ` Borislav Petkov
2022-11-11 12:40 ` Thadeu Lima de Souza Cascardo
2022-11-12 0:46 ` Kim Phillips
2022-11-12 0:54 ` Jim Mattson
2022-11-05 11:39 ` David Laight
2022-11-07 22:40 ` Kim Phillips
2022-11-04 21:36 ` Kim Phillips [this message]
2022-11-04 22:00 ` [PATCH 3/3] x86/speculation: Support Automatic IBRS under virtualization Jim Mattson
2022-11-07 22:29 ` Kim Phillips
2022-11-07 22:42 ` Jim Mattson
2022-11-08 22:48 ` Kim Phillips
2022-11-08 22:59 ` Jim Mattson
2022-11-06 8:38 ` Paolo Bonzini
2022-11-04 22:06 ` [PATCH 0/3] x86/speculation: Support Automatic IBRS Dave Hansen
2022-11-07 22:43 ` Kim Phillips
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