From: Jisheng Zhang <jszhang@kernel.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Jiri Slaby <jirislaby@kernel.org>
Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree
Date: Sun, 20 Nov 2022 16:21:12 +0800 [thread overview]
Message-ID: <20221120082114.3030-6-jszhang@kernel.org> (raw)
In-Reply-To: <20221120082114.3030-1-jszhang@kernel.org>
Add a baisc dtsi for the bouffalolab bl808 SoC.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++
2 files changed, 75 insertions(+)
create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..b525467152b2 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+subdir-y += bouffalolab
subdir-y += sifive
subdir-y += starfive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
new file mode 100644
index 000000000000..c98ebb14ee10
--- /dev/null
+++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "bouffalolab,bl808";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ timebase-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ riscv,isa = "rv64imafdc";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ interrupt-parent = <&plic>;
+ dma-noncoherent;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: serial@30002000 {
+ compatible = "bouffalolab,uart";
+ reg = <0x30002000 0x1000>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ plic: interrupt-controller@e0000000 {
+ compatible = "thead,c900-plic";
+ reg = <0xe0000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 0xffffffff>,
+ <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <64>;
+ };
+ };
+};
--
2.37.2
next prev parent reply other threads:[~2022-11-20 8:31 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-20 8:21 [PATCH 0/7] riscv: add Bouffalolab bl808 support Jisheng Zhang
2022-11-20 8:21 ` [PATCH 1/7] dt-bindings: serial: add bindings doc for Bouffalolab uart driver Jisheng Zhang
2022-11-21 10:08 ` Krzysztof Kozlowski
2022-11-30 18:04 ` Rob Herring
2022-11-20 8:21 ` [PATCH 2/7] serial: bflb_uart: add Bouffalolab UART Driver Jisheng Zhang
2022-11-21 8:09 ` Jiri Slaby
2022-11-21 13:59 ` Ilpo Järvinen
2022-11-20 8:21 ` [PATCH 3/7] MAINTAINERS: add myself as a reviewer for Bouffalolab uart driver Jisheng Zhang
2022-11-20 8:21 ` [PATCH 4/7] riscv: add the Bouffalolab SoC family Kconfig option Jisheng Zhang
2022-11-20 10:43 ` Conor Dooley
2022-11-20 8:21 ` Jisheng Zhang [this message]
2022-11-20 11:02 ` [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree Conor Dooley
2022-11-20 11:58 ` Icenowy Zheng
2022-11-20 14:28 ` Conor Dooley
2022-11-20 14:57 ` Emil Renner Berthing
2022-11-20 17:51 ` Conor Dooley
2022-11-20 18:33 ` Emil Renner Berthing
2022-11-21 3:36 ` Icenowy Zheng
2022-11-21 11:25 ` Emil Renner Berthing
2022-11-21 10:09 ` Krzysztof Kozlowski
2022-11-20 8:21 ` [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree Jisheng Zhang
2022-11-20 11:09 ` Conor Dooley
2022-11-20 11:57 ` Icenowy Zheng
2022-11-20 15:06 ` Emil Renner Berthing
2022-11-21 10:10 ` Krzysztof Kozlowski
2022-11-20 8:21 ` [PATCH 7/7] MAINTAINERS: add myself as Bouffalolab SoC entry maintainer Jisheng Zhang
2022-11-21 10:11 ` Krzysztof Kozlowski
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