From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: martin.petersen@oracle.com, jejb@linux.ibm.com,
andersson@kernel.org, vkoul@kernel.org
Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org,
dmitry.baryshkov@linaro.org, ahalaney@redhat.com,
abel.vesa@linaro.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v3 03/20] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct
Date: Wed, 23 Nov 2022 13:18:09 +0530 [thread overview]
Message-ID: <20221123074826.95369-4-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org>
As done for Qcom PCIe PHY driver, let's move the register settings to the
common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY
settings needed for functionalities like HS-G4 in the future by adding one
more instance of the qmp_phy_cfg_tbls.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 192 ++++++++++++++----------
1 file changed, 112 insertions(+), 80 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 443f2714a8f1..3b7b36e32f5d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -531,19 +531,24 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
};
+struct qmp_phy_cfg_tbls {
+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
+ const struct qmp_phy_init_tbl *serdes;
+ int serdes_num;
+ const struct qmp_phy_init_tbl *tx;
+ int tx_num;
+ const struct qmp_phy_init_tbl *rx;
+ int rx_num;
+ const struct qmp_phy_init_tbl *pcs;
+ int pcs_num;
+};
+
/* struct qmp_phy_cfg - per-PHY initialization config */
struct qmp_phy_cfg {
int lanes;
- /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
- const struct qmp_phy_init_tbl *serdes_tbl;
- int serdes_tbl_num;
- const struct qmp_phy_init_tbl *tx_tbl;
- int tx_tbl_num;
- const struct qmp_phy_init_tbl *rx_tbl;
- int rx_tbl_num;
- const struct qmp_phy_init_tbl *pcs_tbl;
- int pcs_tbl_num;
+ /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
+ const struct qmp_phy_cfg_tbls tbls;
/* clock ids to be requested */
const char * const *clk_list;
@@ -660,12 +665,14 @@ static const char * const qmp_phy_vreg_l[] = {
static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
.lanes = 1,
- .serdes_tbl = msm8996_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
- .tx_tbl = msm8996_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_tx),
- .rx_tbl = msm8996_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_rx),
+ .tbls = {
+ .serdes = msm8996_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
+ .tx = msm8996_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(msm8996_ufsphy_tx),
+ .rx = msm8996_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx),
+ },
.clk_list = msm8996_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
@@ -685,14 +692,16 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.lanes = 2,
- .serdes_tbl = sdm845_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
- .tx_tbl = sdm845_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx),
- .rx_tbl = sdm845_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx),
- .pcs_tbl = sdm845_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
+ .tbls = {
+ .serdes = sdm845_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
+ .tx = sdm845_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
+ .rx = sdm845_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx),
+ .pcs = sdm845_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -709,14 +718,16 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
.lanes = 1,
- .serdes_tbl = sm6115_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
- .tx_tbl = sm6115_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx),
- .rx_tbl = sm6115_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx),
- .pcs_tbl = sm6115_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm6115_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
+ .tx = sm6115_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx),
+ .rx = sm6115_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx),
+ .pcs = sm6115_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -732,14 +743,16 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.lanes = 2,
- .serdes_tbl = sm8150_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
- .tx_tbl = sm8150_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx),
- .rx_tbl = sm8150_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx),
- .pcs_tbl = sm8150_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm8150_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
+ .tx = sm8150_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
+ .rx = sm8150_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
+ .pcs = sm8150_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -754,14 +767,16 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.lanes = 2,
- .serdes_tbl = sm8350_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
- .tx_tbl = sm8350_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
- .rx_tbl = sm8350_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
- .pcs_tbl = sm8350_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm8350_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
+ .tx = sm8350_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
+ .rx = sm8350_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
+ .pcs = sm8350_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -776,14 +791,16 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.lanes = 2,
- .serdes_tbl = sm8350_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
- .tx_tbl = sm8350_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
- .rx_tbl = sm8350_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
- .pcs_tbl = sm8350_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm8350_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
+ .tx = sm8350_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
+ .rx = sm8350_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
+ .pcs = sm8350_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ },
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -826,16 +843,50 @@ static void qmp_ufs_configure(void __iomem *base,
qmp_ufs_configure_lane(base, regs, tbl, num, 0xff);
}
-static int qmp_ufs_serdes_init(struct qmp_phy *qphy)
+static void qmp_ufs_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tbls *tbls)
{
const struct qmp_phy_cfg *cfg = qphy->cfg;
void __iomem *serdes = qphy->serdes;
- const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
- int serdes_tbl_num = cfg->serdes_tbl_num;
- qmp_ufs_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
+ if (!tbls)
+ return;
+
+ qmp_ufs_configure(serdes, cfg->regs, tbls->serdes, tbls->serdes_num);
+}
- return 0;
+static void qmp_ufs_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tbls *tbls)
+{
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *tx = qphy->tx;
+ void __iomem *rx = qphy->rx;
+
+ qmp_ufs_configure_lane(tx, cfg->regs, tbls->tx, tbls->tx_num, 1);
+
+ if (cfg->lanes >= 2)
+ qmp_ufs_configure_lane(qphy->tx2, cfg->regs, tbls->tx, tbls->tx_num, 2);
+
+ qmp_ufs_configure_lane(rx, cfg->regs, tbls->rx, tbls->rx_num, 1);
+
+ if (cfg->lanes >= 2)
+ qmp_ufs_configure_lane(qphy->rx2, cfg->regs, tbls->rx, tbls->rx_num, 2);
+}
+
+static void qmp_ufs_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tbls *tbls)
+{
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *pcs = qphy->pcs;
+
+ if (!tbls)
+ return;
+
+ qmp_ufs_configure(pcs, cfg->regs, tbls->pcs, tbls->pcs_num);
+}
+
+static void qmp_ufs_init_registers(struct qmp_phy *qphy, const struct qmp_phy_cfg *cfg)
+{
+ qmp_ufs_serdes_init(qphy, &cfg->tbls);
+ qmp_ufs_lanes_init(qphy, &cfg->tbls);
+ qmp_ufs_pcs_init(qphy, &cfg->tbls);
}
static int qmp_ufs_com_init(struct qmp_phy *qphy)
@@ -933,31 +984,12 @@ static int qmp_ufs_power_on(struct phy *phy)
struct qmp_phy *qphy = phy_get_drvdata(phy);
struct qcom_qmp *qmp = qphy->qmp;
const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *tx = qphy->tx;
- void __iomem *rx = qphy->rx;
void __iomem *pcs = qphy->pcs;
void __iomem *status;
unsigned int mask, val, ready;
int ret;
- qmp_ufs_serdes_init(qphy);
-
- /* Tx, Rx, and PCS configurations */
- qmp_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1);
-
- if (cfg->lanes >= 2) {
- qmp_ufs_configure_lane(qphy->tx2, cfg->regs,
- cfg->tx_tbl, cfg->tx_tbl_num, 2);
- }
-
- qmp_ufs_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1);
-
- if (cfg->lanes >= 2) {
- qmp_ufs_configure_lane(qphy->rx2, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 2);
- }
-
- qmp_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
+ qmp_ufs_init_registers(qphy, cfg);
ret = reset_control_deassert(qmp->ufs_reset);
if (ret)
--
2.25.1
next prev parent reply other threads:[~2022-11-23 7:49 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-23 7:48 [PATCH v3 00/20] ufs: qcom: Add HS-G4 support Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 01/20] phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl definitions Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 02/20] phy: qcom-qmp-ufs: Rename MSM8996 PHY definitions Manivannan Sadhasivam
2022-11-23 7:48 ` Manivannan Sadhasivam [this message]
2022-11-23 7:48 ` [PATCH v3 04/20] phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 05/20] phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 06/20] phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_b Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 07/20] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoC Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 08/20] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 09/20] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 10/20] scsi: ufs: ufs-qcom: Remove un-necessary goto statements Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 11/20] scsi: ufs: ufs-qcom: Remove un-necessary WARN_ON() Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 12/20] scsi: ufs: ufs-qcom: Use bitfields where appropriate Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 13/20] scsi: ufs: ufs-qcom: Use dev_err_probe() for printing probe error Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 14/20] scsi: ufs: ufs-qcom: Fix the Qcom register name for offset 0xD0 Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 15/20] scsi: ufs: core: Add reinit_notify() callback Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 16/20] scsi: ufs: core: Add support for reinitializing the UFS device Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 17/20] scsi: ufs: ufs-qcom: Factor out the logic finding the HS Gear Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 18/20] scsi: ufs: ufs-qcom: Add support for reinitializing the UFS device Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 19/20] scsi: ufs: ufs-qcom: Add support for finding max gear on new platforms Manivannan Sadhasivam
2022-11-23 7:48 ` [PATCH v3 20/20] MAINTAINERS: Add myself as the maintainer for Qcom UFS driver Manivannan Sadhasivam
2022-11-23 18:31 ` Eric Biggers
2022-11-24 10:13 ` Manivannan Sadhasivam
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