From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 578F2C433FE for ; Wed, 23 Nov 2022 11:09:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236241AbiKWLJK (ORCPT ); Wed, 23 Nov 2022 06:09:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236632AbiKWLI3 (ORCPT ); Wed, 23 Nov 2022 06:08:29 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 321EE78D69 for ; Wed, 23 Nov 2022 03:08:09 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id j5-20020a05600c410500b003cfa9c0ea76so1036725wmi.3 for ; Wed, 23 Nov 2022 03:08:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7EJrTQIS5zIHcJVe/CbMMVgFbpImlTtQ6/Fo8uf0cQs=; b=rMOx5MBKnoMO8ZWepAQQOy+jX4OvsCjUIHSpwMHYbP+cYsRfQDCfrwAHDWASg8vhhM QMWejBaaSthxX85i5r2D2HCPyG+RK2GGaFDu5TnFXGv8QEF5joobcomJiES1GzOXm43J kBqHbTNoHsrPM/Ld8JJGb7y7czcK3OH72xFWbcaQu3EvTTVymJSbOPfpVmHfrbrKcmjz bLuRaedG5M1RX/nQcCt76WABWb/O5jnZIkMVbJl0BJG6xVdBbHX45uJ8vWVz3sY0yogk gXecqUhOSzuhTBy5RkrBKZDu4WKBUtQfAu2/ZctnJ9nGwJ8HwYO/J2IIAmI+wskAEO+O 2grg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7EJrTQIS5zIHcJVe/CbMMVgFbpImlTtQ6/Fo8uf0cQs=; b=Ih/XzBo51NZFpVr01T0Fv52GDHKiE1Oyh3jjrftaN7TxiqQovHBFMFQjWixWIL8KHh zB8jZdMbXvRYxy5cEuzJAyyCuRAxDYV4qnUDZbCPuyo6mwxRoQlR0/00vd6sCcGiNNGC oFc39AQpHRojQshB6NX9saqnmFiFEdjdv8SPr1PP7CE4VvDM++CxYJQMhx1kT9bUtl/c vZqsytWBYW+XucQoNk/8OqTZ7wcg+IwoF+u7Y7W8Kd6t98KNOlsqFfjgaRit+rn1sqFo yJpYVpB2fULpZVkeXq6Lgffc1+yXrrP5W3fISeRBFMmBXq1mB6tT5Mkb0XJXRxrgxmWd cp8w== X-Gm-Message-State: ANoB5plK3B++TP6DOLGJ6y1RLCXOdK/Sjkn/nvm9mW4KRz8o5oBQGfei 2STFs/dwb/0WuHy0fImGA9ljZQ== X-Google-Smtp-Source: AA0mqf7wYQo4Qun3PkdsjrwHo8g+Ckn/I7FTjZZAuskaOkESB8IUYPgLqMkLfk7QmCTuvlqaH8UMbQ== X-Received: by 2002:a05:600c:4f93:b0:3cf:a616:ccc0 with SMTP id n19-20020a05600c4f9300b003cfa616ccc0mr23819082wmq.73.1669201687597; Wed, 23 Nov 2022 03:08:07 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:ae74:d94f:4677:3378]) by smtp.gmail.com with ESMTPSA id f13-20020a05600c4e8d00b003c6c182bef9sm2560406wmq.36.2022.11.23.03.08.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 03:08:07 -0800 (PST) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Srinivas Kandagatla , Vinod Koul , Alex Elder , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, Bartosz Golaszewski , Konrad Dybcio Subject: [PATCH v3 03/13] tty: serial: qcom-geni-serial: align #define values Date: Wed, 23 Nov 2022 12:07:49 +0100 Message-Id: <20221123110759.1836666-4-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221123110759.1836666-1-brgl@bgdev.pl> References: <20221123110759.1836666-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bartosz Golaszewski Keep the #define symbols aligned for better readability. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- drivers/tty/serial/qcom_geni_serial.c | 62 +++++++++++++-------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 7af5df6833c7..97ee7c074b79 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -39,57 +39,57 @@ #define SE_UART_MANUAL_RFR 0x2ac /* SE_UART_TRANS_CFG */ -#define UART_TX_PAR_EN BIT(0) -#define UART_CTS_MASK BIT(1) +#define UART_TX_PAR_EN BIT(0) +#define UART_CTS_MASK BIT(1) /* SE_UART_TX_STOP_BIT_LEN */ -#define TX_STOP_BIT_LEN_1 0 -#define TX_STOP_BIT_LEN_2 2 +#define TX_STOP_BIT_LEN_1 0 +#define TX_STOP_BIT_LEN_2 2 /* SE_UART_RX_TRANS_CFG */ -#define UART_RX_PAR_EN BIT(3) +#define UART_RX_PAR_EN BIT(3) /* SE_UART_RX_WORD_LEN */ -#define RX_WORD_LEN_MASK GENMASK(9, 0) +#define RX_WORD_LEN_MASK GENMASK(9, 0) /* SE_UART_RX_STALE_CNT */ -#define RX_STALE_CNT GENMASK(23, 0) +#define RX_STALE_CNT GENMASK(23, 0) /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ -#define PAR_CALC_EN BIT(0) -#define PAR_EVEN 0x00 -#define PAR_ODD 0x01 -#define PAR_SPACE 0x10 +#define PAR_CALC_EN BIT(0) +#define PAR_EVEN 0x00 +#define PAR_ODD 0x01 +#define PAR_SPACE 0x10 /* SE_UART_MANUAL_RFR register fields */ -#define UART_MANUAL_RFR_EN BIT(31) -#define UART_RFR_NOT_READY BIT(1) -#define UART_RFR_READY BIT(0) +#define UART_MANUAL_RFR_EN BIT(31) +#define UART_RFR_NOT_READY BIT(1) +#define UART_RFR_READY BIT(0) /* UART M_CMD OP codes */ -#define UART_START_TX 0x1 +#define UART_START_TX 0x1 /* UART S_CMD OP codes */ -#define UART_START_READ 0x1 - -#define UART_OVERSAMPLING 32 -#define STALE_TIMEOUT 16 -#define DEFAULT_BITS_PER_CHAR 10 -#define GENI_UART_CONS_PORTS 1 -#define GENI_UART_PORTS 3 -#define DEF_FIFO_DEPTH_WORDS 16 -#define DEF_TX_WM 2 -#define DEF_FIFO_WIDTH_BITS 32 -#define UART_RX_WM 2 +#define UART_START_READ 0x1 + +#define UART_OVERSAMPLING 32 +#define STALE_TIMEOUT 16 +#define DEFAULT_BITS_PER_CHAR 10 +#define GENI_UART_CONS_PORTS 1 +#define GENI_UART_PORTS 3 +#define DEF_FIFO_DEPTH_WORDS 16 +#define DEF_TX_WM 2 +#define DEF_FIFO_WIDTH_BITS 32 +#define UART_RX_WM 2 /* SE_UART_LOOPBACK_CFG */ -#define RX_TX_SORTED BIT(0) -#define CTS_RTS_SORTED BIT(1) -#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) +#define RX_TX_SORTED BIT(0) +#define CTS_RTS_SORTED BIT(1) +#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) /* UART pin swap value */ -#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) +#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) #define IO_MACRO_IO0_SEL 0x3 -#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) +#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) #define IO_MACRO_IO2_IO3_SWAP 0x4640 /* We always configure 4 bytes per FIFO word */ -- 2.37.2