From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40169C4332F for ; Wed, 23 Nov 2022 19:51:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239413AbiKWTvR (ORCPT ); Wed, 23 Nov 2022 14:51:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238951AbiKWTuk (ORCPT ); Wed, 23 Nov 2022 14:50:40 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4777397A8C for ; Wed, 23 Nov 2022 11:50:32 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id o30so13861406wms.2 for ; Wed, 23 Nov 2022 11:50:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=JOkIyMrj9jAVnq1u2b/d95NeRDzS4KUPTPtP8tjZN5c=; b=izKXkVtAN18HUUgc5honLfvEMnEKKEiYpw6rr5QhCHZSz4YMV3zGtEpk4Kw9KDa9aB lzIBNWGpumf24AZIKx1UGOVHKJq2ASnBB1WzQiSg0hHYYqhW55qe8Mou7h0oSU6DRBI9 8oQ+1YTfROqoJ8FQhZF0hJhYSZPpuMG2PDYxjTMa8Yvn/QDR/AQKk4Ch7F5/zjeVUJw9 zwnQtRT/nplooWelf/tAUAxSSNCcNYzSVRvD4v4Njrg3Qd+fcxK4VagLkXsLhzmUS5WA v83E9YNcsUAYOuHsJNfQQkbjpePKfuXkkuriN1bp0JUgETljm75OZxL8qKCCy5SP0M9E AShw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=JOkIyMrj9jAVnq1u2b/d95NeRDzS4KUPTPtP8tjZN5c=; b=wn18YfnE/amdkcmg7BjaFRys1wK7UZHvD0QPPY3KIQjigqkxQxkT3gXEsXBT7xl1mb mKs11ook0VZT1aUcd6Gidyku1tyxWJXkH/fhBT8No63SlHWOCLQdohVvy/pExdPoN2u3 ZZGu4+JCkefMkcQqYyhdX/jLZEWd7J40gGU+NtRi8smJnB+sZL6uSnSpDNPHu3UaDxtq CjwdHrW0o1aOSXeDxx+EeQXdron/Dq8dwMmzJ12p9LiD1QCSn+K7bdX01hVj6EInWXQF O2ROG6TNNzndAnlIRbi3l9nsQchZ4kUFd/nohvRB8wuOKoM6y+AQKtGM1zhv4wFJIRQY yOVw== X-Gm-Message-State: ANoB5pmGRqT6Vjjvz/KtxtkaUdDvPZoWHm/JIh3wLCXw/fHpAgmfDi2y OrA7S+T/t9O9MGagcVh5Z/FLTw== X-Google-Smtp-Source: AA0mqf41X2s36JH0hfgDJwcvdifZ6rKZMBeU0YLHrAPXohfNW8unSCpgvwT9u0P7iyuG8iyUol8whQ== X-Received: by 2002:a05:600c:35d4:b0:3cf:84e9:e722 with SMTP id r20-20020a05600c35d400b003cf84e9e722mr20697519wmq.8.1669233031852; Wed, 23 Nov 2022 11:50:31 -0800 (PST) Received: from linaro.org ([2a00:23c5:6809:2201:fcbc:7b5d:8d6c:43a4]) by smtp.gmail.com with ESMTPSA id w5-20020a5d6805000000b002364c77bcacsm7267414wru.38.2022.11.23.11.50.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 11:50:31 -0800 (PST) From: Mike Leach To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-perf-users@vger.kernel.org, leo.yan@linaro.org, quic_jinlmao@quicinc.com, Mike Leach Subject: [PATCH v6 10/14] perf: cs-etm: Update record event to use new Trace ID protocol Date: Wed, 23 Nov 2022 19:50:06 +0000 Message-Id: <20221123195010.6859-11-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123195010.6859-1-mike.leach@linaro.org> References: <20221123195010.6859-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Trace IDs are now dynamically allocated. Previously used the static association algorithm that is no longer used. The 'cpu * 2 + seed' was outdated and broken for systems with high core counts (>46). as it did not scale and was broken for larger core counts. Trace ID will now be sent in PERF_RECORD_AUX_OUTPUT_HW_ID record. Legacy ID algorithm renamed and retained for limited backward compatibility use. Signed-off-by: Mike Leach Reviewed-by: James Clark Acked-by: Suzuki K Poulose --- tools/include/linux/coresight-pmu.h | 30 +++++++++++++++++------------ tools/perf/arch/arm/util/cs-etm.c | 21 ++++++++++++-------- 2 files changed, 31 insertions(+), 20 deletions(-) diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index db9c7c0abb6a..307f357defe9 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -10,11 +10,28 @@ #include #define CORESIGHT_ETM_PMU_NAME "cs_etm" -#define CORESIGHT_ETM_PMU_SEED 0x10 + +/* + * The legacy Trace ID system based on fixed calculation from the cpu + * number. This has been replaced by drivers using a dynamic allocation + * system - but need to retain the legacy algorithm for backward comparibility + * in certain situations:- + * a) new perf running on older systems that generate the legacy mapping + * b) older tools e.g. simpleperf in Android, that may not update at the same + * time as the kernel. + */ +#define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2)) /* CoreSight trace ID is currently the bottom 7 bits of the value */ #define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0) +/* + * perf record will set the legacy meta data values as unused initially. + * This allows perf report to manage the decoders created when dynamic + * allocation in operation. + */ +#define CORESIGHT_TRACE_ID_UNUSED_FLAG BIT(31) + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. @@ -39,15 +56,4 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 -static inline int coresight_get_trace_id(int cpu) -{ - /* - * A trace ID of value 0 is invalid, so let's start at some - * random value that fits in 7 bits and go from there. Since - * the common convention is to have data trace IDs be I(N) + 1, - * set instruction trace IDs as a function of the CPU number. - */ - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); -} - #endif diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index a346d5f3dafa..c7e4b543259f 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -421,13 +421,16 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, evlist__to_front(evlist, cs_etm_evsel); /* - * In the case of per-cpu mmaps, we need the CPU on the - * AUX event. We also need the contextID in order to be notified + * get the CPU on the sample - need it to associate trace ID in the + * AUX_OUTPUT_HW_ID event, and the AUX event for per-cpu mmaps. + */ + evsel__set_sample_bit(cs_etm_evsel, CPU); + + /* + * Also the case of per-cpu mmaps, need the contextID in order to be notified * when a context switch happened. */ if (!perf_cpu_map__empty(cpus)) { - evsel__set_sample_bit(cs_etm_evsel, CPU); - err = cs_etm_set_option(itr, cs_etm_evsel, BIT(ETM_OPT_CTXTID) | BIT(ETM_OPT_TS)); if (err) @@ -633,8 +636,10 @@ static void cs_etm_save_etmv4_header(__u64 data[], struct auxtrace_record *itr, /* Get trace configuration register */ data[CS_ETMV4_TRCCONFIGR] = cs_etmv4_get_config(itr); - /* Get traceID from the framework */ - data[CS_ETMV4_TRCTRACEIDR] = coresight_get_trace_id(cpu); + /* traceID set to legacy version, in case new perf running on older system */ + data[CS_ETMV4_TRCTRACEIDR] = + CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) | CORESIGHT_TRACE_ID_UNUSED_FLAG; + /* Get read-only information from sysFS */ data[CS_ETMV4_TRCIDR0] = cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0]); @@ -681,9 +686,9 @@ static void cs_etm_get_metadata(int cpu, u32 *offset, magic = __perf_cs_etmv3_magic; /* Get configuration register */ info->priv[*offset + CS_ETM_ETMCR] = cs_etm_get_config(itr); - /* Get traceID from the framework */ + /* traceID set to legacy value in case new perf running on old system */ info->priv[*offset + CS_ETM_ETMTRACEIDR] = - coresight_get_trace_id(cpu); + CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) | CORESIGHT_TRACE_ID_UNUSED_FLAG; /* Get read-only information from sysFS */ info->priv[*offset + CS_ETM_ETMCCER] = cs_etm_get_ro(cs_etm_pmu, cpu, -- 2.17.1