From: Chester Lin <clin@suse.com>
To: Giuseppe Cavallaro <peppe.cavallaro@st.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Jose Abreu <joabreu@synopsys.com>
Cc: "Chester Lin" <clin@suse.com>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
"David S. Miller" <davem@davemloft.net>,
"Eric Dumazet" <edumazet@google.com>,
"Jakub Kicinski" <kuba@kernel.org>,
"Paolo Abeni" <pabeni@redhat.com>,
"Jan Petrous" <jan.petrous@nxp.com>,
"Ondrej Spacek" <ondrej.spacek@nxp.com>,
"Andreas Färber" <afaerber@suse.de>,
"Matthias Brugger" <mbrugger@suse.com>
Subject: [PATCH v2 4/5] net: stmmac: Add AXI4 ACE control support
Date: Mon, 28 Nov 2022 13:49:19 +0800 [thread overview]
Message-ID: <20221128054920.2113-5-clin@suse.com> (raw)
In-Reply-To: <20221128054920.2113-1-clin@suse.com>
Add AXI4 cache coherency control in dwmac4 DMA core.
Signed-off-by: Ondrej Spacek <ondrej.spacek@nxp.com>
Signed-off-by: Chester Lin <clin@suse.com>
---
No change in v2.
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 10 ++++++++++
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h | 4 +++-
drivers/net/ethernet/stmicro/stmmac/hwif.h | 5 +++++
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 3 +++
include/linux/stmmac.h | 7 +++++++
5 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
index d99fa028c646..4e6e2952abfd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
@@ -517,6 +517,15 @@ static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)
return 0;
}
+static void dwmac4_axi4_cc(void __iomem *ioaddr,
+ struct stmmac_axi4_ace_ctrl *acecfg)
+{
+ /* Configure AXI4 cache coherency for Tx/Rx DMA channels */
+ writel(acecfg->tx_ar_reg, ioaddr + DMA_AXI4_TX_AR_ACE_CONTROL);
+ writel(acecfg->rx_aw_reg, ioaddr + DMA_AXI4_RX_AW_ACE_CONTROL);
+ writel(acecfg->txrx_awar_reg, ioaddr + DMA_AXI4_TXRX_AWAR_ACE_CONTROL);
+}
+
const struct stmmac_dma_ops dwmac4_dma_ops = {
.reset = dwmac4_dma_reset,
.init = dwmac4_dma_init,
@@ -574,4 +583,5 @@ const struct stmmac_dma_ops dwmac410_dma_ops = {
.set_bfsize = dwmac4_set_bfsize,
.enable_sph = dwmac4_enable_sph,
.enable_tbs = dwmac4_enable_tbs,
+ .axi4_cc = dwmac4_axi4_cc,
};
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
index 9321879b599c..7f491f2651b2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
@@ -21,7 +21,9 @@
#define DMA_DEBUG_STATUS_0 0x0000100c
#define DMA_DEBUG_STATUS_1 0x00001010
#define DMA_DEBUG_STATUS_2 0x00001014
-#define DMA_AXI_BUS_MODE 0x00001028
+#define DMA_AXI4_TX_AR_ACE_CONTROL 0x00001020
+#define DMA_AXI4_RX_AW_ACE_CONTROL 0x00001024
+#define DMA_AXI4_TXRX_AWAR_ACE_CONTROL 0x00001028
#define DMA_TBS_CTRL 0x00001050
/* DMA Bus Mode bitmap */
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h
index 592b4067f9b8..bffe2ec36bb3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.h
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h
@@ -212,6 +212,9 @@ struct stmmac_dma_ops {
void (*set_bfsize)(void __iomem *ioaddr, int bfsize, u32 chan);
void (*enable_sph)(void __iomem *ioaddr, bool en, u32 chan);
int (*enable_tbs)(void __iomem *ioaddr, bool en, u32 chan);
+ /* Configure AXI4 cache coherency for Tx and Rx DMA channels */
+ void (*axi4_cc)(void __iomem *ioaddr,
+ struct stmmac_axi4_ace_ctrl *acecfg);
};
#define stmmac_reset(__priv, __args...) \
@@ -272,6 +275,8 @@ struct stmmac_dma_ops {
stmmac_do_void_callback(__priv, dma, enable_sph, __args)
#define stmmac_enable_tbs(__priv, __args...) \
stmmac_do_callback(__priv, dma, enable_tbs, __args)
+#define stmmac_axi4_cc(__priv, __args...) \
+ stmmac_do_void_callback(__priv, dma, axi4_cc, __args)
struct mac_device_info;
struct net_device;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index ff0b32c9e748..c689723c7d93 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -2917,6 +2917,9 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv)
if (priv->plat->axi)
stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
+ if (priv->plat->axi4_ace_ctrl)
+ stmmac_axi4_cc(priv, priv->ioaddr, priv->plat->axi4_ace_ctrl);
+
/* DMA CSR Channel configuration */
for (chan = 0; chan < dma_csr_ch; chan++) {
stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 307980c808f7..23e740c6c7b8 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -115,6 +115,12 @@ struct stmmac_axi {
bool axi_rb;
};
+struct stmmac_axi4_ace_ctrl {
+ u32 tx_ar_reg;
+ u32 rx_aw_reg;
+ u32 txrx_awar_reg;
+};
+
#define EST_GCL 1024
struct stmmac_est {
struct mutex lock;
@@ -248,6 +254,7 @@ struct plat_stmmacenet_data {
struct reset_control *stmmac_rst;
struct reset_control *stmmac_ahb_rst;
struct stmmac_axi *axi;
+ struct stmmac_axi4_ace_ctrl *axi4_ace_ctrl;
int has_gmac4;
bool has_sun8i;
bool tso_en;
--
2.37.3
next prev parent reply other threads:[~2022-11-28 5:50 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-28 5:49 [PATCH v2 0/5] Add GMAC support for S32 SoC family Chester Lin
2022-11-28 5:49 ` [PATCH v2 1/5] dt-bindings: net: snps, dwmac: add NXP S32CC support Chester Lin
2022-11-29 14:10 ` Andreas Färber
2022-11-28 5:49 ` [PATCH v2 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver Chester Lin
2022-11-30 15:51 ` Krzysztof Kozlowski
2022-11-30 17:33 ` Andreas Färber
2022-11-30 18:14 ` Andrew Lunn
2022-12-01 10:18 ` Krzysztof Kozlowski
2022-12-05 7:54 ` Chester Lin
2022-12-05 8:55 ` Krzysztof Kozlowski
2022-12-13 2:46 ` Chester Lin
2022-12-13 7:50 ` Krzysztof Kozlowski
2022-11-28 5:49 ` [PATCH v2 3/5] net: stmmac: Add CSR clock 500Mhz/800Mhz support Chester Lin
2022-11-28 5:49 ` Chester Lin [this message]
2022-11-28 5:49 ` [PATCH v2 5/5] net: stmmac: Add NXP S32 SoC family support Chester Lin
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