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* [PATCH v4 0/7] Support for the NPU in Vim3
@ 2022-12-01  9:21 Tomeu Vizoso
  2022-12-01  9:21 ` [PATCH v4 1/7] dt-bindings: reset: meson-g12a: Add missing NNA reset Tomeu Vizoso
                   ` (6 more replies)
  0 siblings, 7 replies; 9+ messages in thread
From: Tomeu Vizoso @ 2022-12-01  9:21 UTC (permalink / raw)
  Cc: italonicola, Tomeu Vizoso, Christian Gmeiner, Daniel Vetter,
	David Airlie,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list:DRM DRIVERS FOR VIVANTE GPU IP,
	moderated list:DRM DRIVERS FOR VIVANTE GPU IP, Jerome Brunet,
	Kevin Hilman, Krzysztof Kozlowski,
	open list:ARM/Amlogic Meson SoC support,
	moderated list:ARM/Amlogic Meson SoC support, open list,
	Lucas Stach, Martin Blumenstingl, Neil Armstrong, Philipp Zabel,
	Rob Herring, Russell King

Hi,

This series adds support for the Verisilicon VIPNano-QI NPU in the A311D
as in the VIM3 board.

The IP is very closely based on previous Vivante GPUs, so the etnaviv
kernel driver works basically unchanged.

The userspace part of the driver is being reviewed at:

https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18986

v2: Move reference to RESET_NNA to npu node (Neil)
v3: Fix indentation mistake (Neil)
v4: Add warning when etnaviv probes on a NPU

Regards,

Tomeu

Tomeu Vizoso (7):
  dt-bindings: reset: meson-g12a: Add missing NNA reset
  dt-bindings: power: Add G12A NNA power domain
  soc: amlogic: meson-pwrc: Add NNA power domain for A311D
  arm64: dts: Add DT node for the VIPNano-QI on the A311D
  drm/etnaviv: add HWDB entry for VIPNano-QI.7120.0055
  drm/etnaviv: Add nn_core_count to chip feature struct
  drm/etnaviv: Warn when probing on NPUs

 .../boot/dts/amlogic/meson-g12-common.dtsi    | 11 ++++++
 .../amlogic/meson-g12b-a311d-khadas-vim3.dts  |  4 +++
 drivers/gpu/drm/etnaviv/etnaviv_gpu.c         |  4 +++
 drivers/gpu/drm/etnaviv/etnaviv_gpu.h         |  3 ++
 drivers/gpu/drm/etnaviv/etnaviv_hwdb.c        | 36 +++++++++++++++++++
 drivers/soc/amlogic/meson-ee-pwrc.c           | 17 +++++++++
 include/dt-bindings/power/meson-g12a-power.h  |  1 +
 .../reset/amlogic,meson-g12a-reset.h          |  4 ++-
 8 files changed, 79 insertions(+), 1 deletion(-)

-- 
2.38.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v4 1/7] dt-bindings: reset: meson-g12a: Add missing NNA reset
  2022-12-01  9:21 [PATCH v4 0/7] Support for the NPU in Vim3 Tomeu Vizoso
@ 2022-12-01  9:21 ` Tomeu Vizoso
  2022-12-01  9:21 ` [PATCH v4 2/7] dt-bindings: power: Add G12A NNA power domain Tomeu Vizoso
                   ` (5 subsequent siblings)
  6 siblings, 0 replies; 9+ messages in thread
From: Tomeu Vizoso @ 2022-12-01  9:21 UTC (permalink / raw)
  Cc: italonicola, Tomeu Vizoso, Neil Armstrong, Philipp Zabel,
	Rob Herring, Krzysztof Kozlowski, Kevin Hilman, Jerome Brunet,
	Martin Blumenstingl,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/Amlogic Meson SoC support,
	open list:ARM/Amlogic Meson SoC support, open list

Doesn't appear in the TRM I have, but it is used by the downstream
galcore driver.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 include/dt-bindings/reset/amlogic,meson-g12a-reset.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
index 6d487c5eba2c..45f6b8a951d0 100644
--- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
+++ b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
@@ -69,7 +69,9 @@
 #define RESET_PARSER_FETCH		72
 #define RESET_CTL			73
 #define RESET_PARSER_TOP		74
-/*					75-77	*/
+/*					75	*/
+#define RESET_NNA			76
+/*					77	*/
 #define RESET_DVALIN			78
 #define RESET_HDMITX			79
 /*					80-95	*/
-- 
2.38.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH v4 2/7] dt-bindings: power: Add G12A NNA power domain
  2022-12-01  9:21 [PATCH v4 0/7] Support for the NPU in Vim3 Tomeu Vizoso
  2022-12-01  9:21 ` [PATCH v4 1/7] dt-bindings: reset: meson-g12a: Add missing NNA reset Tomeu Vizoso
@ 2022-12-01  9:21 ` Tomeu Vizoso
  2022-12-01  9:21 ` [PATCH v4 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D Tomeu Vizoso
                   ` (4 subsequent siblings)
  6 siblings, 0 replies; 9+ messages in thread
From: Tomeu Vizoso @ 2022-12-01  9:21 UTC (permalink / raw)
  Cc: italonicola, Tomeu Vizoso, Neil Armstrong, Rob Herring,
	Krzysztof Kozlowski, Kevin Hilman, Jerome Brunet,
	Martin Blumenstingl,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/Amlogic Meson SoC support,
	open list:ARM/Amlogic Meson SoC support, open list

Add define for the NNA power domain for the NPU in the G12A.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 include/dt-bindings/power/meson-g12a-power.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h
index bb5e67a842de..93b03bdd60b7 100644
--- a/include/dt-bindings/power/meson-g12a-power.h
+++ b/include/dt-bindings/power/meson-g12a-power.h
@@ -9,5 +9,6 @@
 
 #define PWRC_G12A_VPU_ID		0
 #define PWRC_G12A_ETH_ID		1
+#define PWRC_G12A_NNA_ID		2
 
 #endif
-- 
2.38.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH v4 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D
  2022-12-01  9:21 [PATCH v4 0/7] Support for the NPU in Vim3 Tomeu Vizoso
  2022-12-01  9:21 ` [PATCH v4 1/7] dt-bindings: reset: meson-g12a: Add missing NNA reset Tomeu Vizoso
  2022-12-01  9:21 ` [PATCH v4 2/7] dt-bindings: power: Add G12A NNA power domain Tomeu Vizoso
@ 2022-12-01  9:21 ` Tomeu Vizoso
  2022-12-01  9:21 ` [PATCH v4 4/7] arm64: dts: Add DT node for the VIPNano-QI on the A311D Tomeu Vizoso
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 9+ messages in thread
From: Tomeu Vizoso @ 2022-12-01  9:21 UTC (permalink / raw)
  Cc: italonicola, Tomeu Vizoso, Neil Armstrong, Kevin Hilman,
	Jerome Brunet, Martin Blumenstingl,
	moderated list:ARM/Amlogic Meson SoC support,
	open list:ARM/Amlogic Meson SoC support, open list

Based on power initialization sequence in downstream driver.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c
index dd5f2a13ceb5..dfbf0b1c7d29 100644
--- a/drivers/soc/amlogic/meson-ee-pwrc.c
+++ b/drivers/soc/amlogic/meson-ee-pwrc.c
@@ -46,6 +46,9 @@
 #define HHI_NANOQ_MEM_PD_REG1		(0x47 << 2)
 #define HHI_VPU_MEM_PD_REG2		(0x4d << 2)
 
+#define G12A_HHI_NANOQ_MEM_PD_REG0	(0x43 << 2)
+#define G12A_HHI_NANOQ_MEM_PD_REG1	(0x44 << 2)
+
 struct meson_ee_pwrc;
 struct meson_ee_pwrc_domain;
 
@@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
 static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
 static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
 
+static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = {	\
+		.sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, 		\
+		.sleep_mask = BIT(16) | BIT(17),		\
+		.iso_reg = GX_AO_RTI_GEN_PWR_ISO0, 		\
+		.iso_mask = BIT(16) | BIT(17), 			\
+	};
+
 /* Memory PD Domains */
 
 #define VPU_MEMPD(__reg)					\
@@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
 };
 
+static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
+	{ G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) },
+	{ G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) },
+};
+
 #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks)	\
 	{								\
 		.name = __name,						\
@@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
 	[PWRC_G12A_VPU_ID]  = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
 				     pwrc_ee_is_powered_off, 11, 2),
 	[PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
+	[PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna,
+				    pwrc_ee_is_powered_off),
 };
 
 static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
-- 
2.38.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH v4 4/7] arm64: dts: Add DT node for the VIPNano-QI on the A311D
  2022-12-01  9:21 [PATCH v4 0/7] Support for the NPU in Vim3 Tomeu Vizoso
                   ` (2 preceding siblings ...)
  2022-12-01  9:21 ` [PATCH v4 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D Tomeu Vizoso
@ 2022-12-01  9:21 ` Tomeu Vizoso
  2022-12-01  9:21 ` [PATCH v4 5/7] drm/etnaviv: add HWDB entry for VIPNano-QI.7120.0055 Tomeu Vizoso
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 9+ messages in thread
From: Tomeu Vizoso @ 2022-12-01  9:21 UTC (permalink / raw)
  Cc: italonicola, Tomeu Vizoso, Neil Armstrong, Rob Herring,
	Krzysztof Kozlowski, Kevin Hilman, Jerome Brunet,
	Martin Blumenstingl,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	moderated list:ARM/Amlogic Meson SoC support,
	open list:ARM/Amlogic Meson SoC support, open list

This "NPU" is very similar to the Vivante GPUs and Etnaviv works well
with it with just a few small changes.

v2: Add reference to RESET_NNA (Neil)
v3: Fix indentation (Neil)

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi     | 11 +++++++++++
 .../boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts |  4 ++++
 2 files changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index 45947c1031c4..61c8461df614 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/meson-g12a-power.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -2484,4 +2485,14 @@ xtal: xtal-clk {
 		#clock-cells = <0>;
 	};
 
+	npu: npu@ff100000 {
+		compatible = "vivante,gc";
+		reg = <0x0 0xff100000 0x0 0x20000>;
+		interrupts = <0 147 4>;
+		clocks = <&clkc CLKID_NNA_CORE_CLK>,
+			 <&clkc CLKID_NNA_AXI_CLK>;
+		clock-names = "core", "bus";
+		resets = <&reset RESET_NNA>;
+		power-domains = <&pwrc PWRC_G12A_NNA_ID>;
+	};
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
index 124a80901084..73f3d87dcefd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
@@ -15,6 +15,10 @@ / {
 	compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b";
 };
 
+&npu {
+	status = "okay";
+};
+
 /*
  * The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
  * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
-- 
2.38.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH v4 5/7] drm/etnaviv: add HWDB entry for VIPNano-QI.7120.0055
  2022-12-01  9:21 [PATCH v4 0/7] Support for the NPU in Vim3 Tomeu Vizoso
                   ` (3 preceding siblings ...)
  2022-12-01  9:21 ` [PATCH v4 4/7] arm64: dts: Add DT node for the VIPNano-QI on the A311D Tomeu Vizoso
@ 2022-12-01  9:21 ` Tomeu Vizoso
  2022-12-01  9:48   ` Lucas Stach
  2022-12-01  9:21 ` [PATCH v4 6/7] drm/etnaviv: Add nn_core_count to chip feature struct Tomeu Vizoso
  2022-12-01  9:21 ` [PATCH v4 7/7] drm/etnaviv: Warn when probing on NPUs Tomeu Vizoso
  6 siblings, 1 reply; 9+ messages in thread
From: Tomeu Vizoso @ 2022-12-01  9:21 UTC (permalink / raw)
  Cc: italonicola, Tomeu Vizoso, Lucas Stach, Russell King,
	Christian Gmeiner, David Airlie, Daniel Vetter,
	moderated list:DRM DRIVERS FOR VIVANTE GPU IP,
	open list:DRM DRIVERS FOR VIVANTE GPU IP, open list

This is a compute-only module marketed towards AI and vision
acceleration. This particular version can be found on the Amlogic A311D
SoC.

The feature bits are taken from the Khadas downstream kernel driver
6.4.4.3.310723AAA.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
---
 drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 31 ++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
index f2fc645c7956..3f6fd9a3c088 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
@@ -130,6 +130,37 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
 		.minor_features10 = 0x90044250,
 		.minor_features11 = 0x00000024,
 	},
+	{
+		.model = 0x8000,
+		.revision = 0x7120,
+		.product_id = 0x45080009,
+		.customer_id = 0x88,
+		.eco_id = 0,
+		.stream_count = 8,
+		.register_max = 64,
+		.thread_count = 256,
+		.shader_core_count = 1,
+		.vertex_cache_size = 16,
+		.vertex_output_buffer_size = 1024,
+		.pixel_pipes = 1,
+		.instruction_count = 512,
+		.num_constants = 320,
+		.buffer_size = 0,
+		.varyings_count = 16,
+		.features = 0xe0287cac,
+		.minor_features0 = 0xc1799eff,
+		.minor_features1 = 0xfefbfadb,
+		.minor_features2 = 0xeb9d6fbf,
+		.minor_features3 = 0xedfffced,
+		.minor_features4 = 0xd30dafc7,
+		.minor_features5 = 0x7b5ac333,
+		.minor_features6 = 0xfc8ee200,
+		.minor_features7 = 0x03fffa6f,
+		.minor_features8 = 0x00fe0ef0,
+		.minor_features9 = 0x0088003c,
+		.minor_features10 = 0x108048c0,
+		.minor_features11 = 0x00000010,
+	},
 };
 
 bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu)
-- 
2.38.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH v4 6/7] drm/etnaviv: Add nn_core_count to chip feature struct
  2022-12-01  9:21 [PATCH v4 0/7] Support for the NPU in Vim3 Tomeu Vizoso
                   ` (4 preceding siblings ...)
  2022-12-01  9:21 ` [PATCH v4 5/7] drm/etnaviv: add HWDB entry for VIPNano-QI.7120.0055 Tomeu Vizoso
@ 2022-12-01  9:21 ` Tomeu Vizoso
  2022-12-01  9:21 ` [PATCH v4 7/7] drm/etnaviv: Warn when probing on NPUs Tomeu Vizoso
  6 siblings, 0 replies; 9+ messages in thread
From: Tomeu Vizoso @ 2022-12-01  9:21 UTC (permalink / raw)
  Cc: italonicola, Tomeu Vizoso, Lucas Stach, Russell King,
	Christian Gmeiner, David Airlie, Daniel Vetter,
	moderated list:DRM DRIVERS FOR VIVANTE GPU IP,
	open list:DRM DRIVERS FOR VIVANTE GPU IP, open list

We will use these for differentiating between GPUs and NPUs, as the
downstream driver does.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
---
 drivers/gpu/drm/etnaviv/etnaviv_gpu.h  | 3 +++
 drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 5 +++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
index 85eddd492774..c8f3ad2031ce 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
@@ -50,6 +50,9 @@ struct etnaviv_chip_identity {
 	/* Number of shader cores. */
 	u32 shader_core_count;
 
+	/* Number of Neural Network cores. */
+	u32 nn_core_count;
+
 	/* Size of the vertex cache. */
 	u32 vertex_cache_size;
 
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
index 3f6fd9a3c088..9fc5223299e4 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
@@ -16,6 +16,7 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
 		.register_max = 64,
 		.thread_count = 128,
 		.shader_core_count = 1,
+		.nn_core_count = 0,
 		.vertex_cache_size = 8,
 		.vertex_output_buffer_size = 1024,
 		.pixel_pipes = 1,
@@ -47,6 +48,7 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
 		.register_max = 64,
 		.thread_count = 512,
 		.shader_core_count = 2,
+		.nn_core_count = 0,
 		.vertex_cache_size = 16,
 		.vertex_output_buffer_size = 1024,
 		.pixel_pipes = 1,
@@ -78,6 +80,7 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
 		.register_max = 64,
 		.thread_count = 512,
 		.shader_core_count = 2,
+		.nn_core_count = 0,
 		.vertex_cache_size = 16,
 		.vertex_output_buffer_size = 1024,
 		.pixel_pipes = 1,
@@ -109,6 +112,7 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
 		.register_max = 64,
 		.thread_count = 1024,
 		.shader_core_count = 4,
+		.nn_core_count = 0,
 		.vertex_cache_size = 16,
 		.vertex_output_buffer_size = 1024,
 		.pixel_pipes = 2,
@@ -140,6 +144,7 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
 		.register_max = 64,
 		.thread_count = 256,
 		.shader_core_count = 1,
+		.nn_core_count = 8,
 		.vertex_cache_size = 16,
 		.vertex_output_buffer_size = 1024,
 		.pixel_pipes = 1,
-- 
2.38.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH v4 7/7] drm/etnaviv: Warn when probing on NPUs
  2022-12-01  9:21 [PATCH v4 0/7] Support for the NPU in Vim3 Tomeu Vizoso
                   ` (5 preceding siblings ...)
  2022-12-01  9:21 ` [PATCH v4 6/7] drm/etnaviv: Add nn_core_count to chip feature struct Tomeu Vizoso
@ 2022-12-01  9:21 ` Tomeu Vizoso
  6 siblings, 0 replies; 9+ messages in thread
From: Tomeu Vizoso @ 2022-12-01  9:21 UTC (permalink / raw)
  Cc: italonicola, Tomeu Vizoso, Lucas Stach, Russell King,
	Christian Gmeiner, David Airlie, Daniel Vetter,
	moderated list:DRM DRIVERS FOR VIVANTE GPU IP,
	open list:DRM DRIVERS FOR VIVANTE GPU IP, open list

Userspace is still not making full use of the hardware, so we don't know
yet if changes to the UAPI won't be needed. Warn about it.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
---
 drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 37018bc55810..3cbc82bbf8d4 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -765,6 +765,10 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 		goto fail;
 	}
 
+	if (gpu->identity.nn_core_count > 0)
+		dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, "
+                                   "for which the UAPI is still experimental\n");
+
 	/* Exclude VG cores with FE2.0 */
 	if (gpu->identity.features & chipFeatures_PIPE_VG &&
 	    gpu->identity.features & chipFeatures_FE20) {
-- 
2.38.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* Re: [PATCH v4 5/7] drm/etnaviv: add HWDB entry for VIPNano-QI.7120.0055
  2022-12-01  9:21 ` [PATCH v4 5/7] drm/etnaviv: add HWDB entry for VIPNano-QI.7120.0055 Tomeu Vizoso
@ 2022-12-01  9:48   ` Lucas Stach
  0 siblings, 0 replies; 9+ messages in thread
From: Lucas Stach @ 2022-12-01  9:48 UTC (permalink / raw)
  To: Tomeu Vizoso
  Cc: italonicola, moderated list:DRM DRIVERS FOR VIVANTE GPU IP,
	open list:DRM DRIVERS FOR VIVANTE GPU IP, open list,
	Christian Gmeiner, Daniel Vetter, Russell King, David Airlie

Hi Tomeu,

the changes itself look good to me now, I was just very confused about
the ordering of the patches.

I would have expected them to be in this order:
1. Add NN cores to chip identities struct (set to 0 for all existing
entries in HWDB)
2. Add UAPI warning
3. Add HWDB entry for VIPNano-QI.7120.0055 (having NN cores set to
correct value, so you don't touch the entry twice in the same series)

Regards,
Lucas

Am Donnerstag, dem 01.12.2022 um 10:21 +0100 schrieb Tomeu Vizoso:
> This is a compute-only module marketed towards AI and vision
> acceleration. This particular version can be found on the Amlogic A311D
> SoC.
> 
> The feature bits are taken from the Khadas downstream kernel driver
> 6.4.4.3.310723AAA.
> 
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> ---
>  drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 31 ++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
> index f2fc645c7956..3f6fd9a3c088 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
> @@ -130,6 +130,37 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
>  		.minor_features10 = 0x90044250,
>  		.minor_features11 = 0x00000024,
>  	},
> +	{
> +		.model = 0x8000,
> +		.revision = 0x7120,
> +		.product_id = 0x45080009,
> +		.customer_id = 0x88,
> +		.eco_id = 0,
> +		.stream_count = 8,
> +		.register_max = 64,
> +		.thread_count = 256,
> +		.shader_core_count = 1,
> +		.vertex_cache_size = 16,
> +		.vertex_output_buffer_size = 1024,
> +		.pixel_pipes = 1,
> +		.instruction_count = 512,
> +		.num_constants = 320,
> +		.buffer_size = 0,
> +		.varyings_count = 16,
> +		.features = 0xe0287cac,
> +		.minor_features0 = 0xc1799eff,
> +		.minor_features1 = 0xfefbfadb,
> +		.minor_features2 = 0xeb9d6fbf,
> +		.minor_features3 = 0xedfffced,
> +		.minor_features4 = 0xd30dafc7,
> +		.minor_features5 = 0x7b5ac333,
> +		.minor_features6 = 0xfc8ee200,
> +		.minor_features7 = 0x03fffa6f,
> +		.minor_features8 = 0x00fe0ef0,
> +		.minor_features9 = 0x0088003c,
> +		.minor_features10 = 0x108048c0,
> +		.minor_features11 = 0x00000010,
> +	},
>  };
>  
>  bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu)



^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2022-12-01  9:48 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-01  9:21 [PATCH v4 0/7] Support for the NPU in Vim3 Tomeu Vizoso
2022-12-01  9:21 ` [PATCH v4 1/7] dt-bindings: reset: meson-g12a: Add missing NNA reset Tomeu Vizoso
2022-12-01  9:21 ` [PATCH v4 2/7] dt-bindings: power: Add G12A NNA power domain Tomeu Vizoso
2022-12-01  9:21 ` [PATCH v4 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D Tomeu Vizoso
2022-12-01  9:21 ` [PATCH v4 4/7] arm64: dts: Add DT node for the VIPNano-QI on the A311D Tomeu Vizoso
2022-12-01  9:21 ` [PATCH v4 5/7] drm/etnaviv: add HWDB entry for VIPNano-QI.7120.0055 Tomeu Vizoso
2022-12-01  9:48   ` Lucas Stach
2022-12-01  9:21 ` [PATCH v4 6/7] drm/etnaviv: Add nn_core_count to chip feature struct Tomeu Vizoso
2022-12-01  9:21 ` [PATCH v4 7/7] drm/etnaviv: Warn when probing on NPUs Tomeu Vizoso

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