From: Tomeu Vizoso <tomeu.vizoso@collabora.com>
To: unlisted-recipients:; (no To-header on input)
Cc: italonicola@collabora.com,
Tomeu Vizoso <tomeu.vizoso@collabora.com>,
Lucas Stach <l.stach@pengutronix.de>,
Russell King <linux+etnaviv@armlinux.org.uk>,
Christian Gmeiner <christian.gmeiner@gmail.com>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
etnaviv@lists.freedesktop.org (moderated list:DRM DRIVERS FOR
VIVANTE GPU IP),
dri-devel@lists.freedesktop.org (open list:DRM DRIVERS FOR
VIVANTE GPU IP), linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v5 5/7] drm/etnaviv: Add nn_core_count to chip feature struct
Date: Thu, 1 Dec 2022 11:30:21 +0100 [thread overview]
Message-ID: <20221201103026.53234-6-tomeu.vizoso@collabora.com> (raw)
In-Reply-To: <20221201103026.53234-1-tomeu.vizoso@collabora.com>
We will use these for differentiating between GPUs and NPUs, as the
downstream driver does.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 3 +++
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
index 85eddd492774..c8f3ad2031ce 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
@@ -50,6 +50,9 @@ struct etnaviv_chip_identity {
/* Number of shader cores. */
u32 shader_core_count;
+ /* Number of Neural Network cores. */
+ u32 nn_core_count;
+
/* Size of the vertex cache. */
u32 vertex_cache_size;
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
index f2fc645c7956..44df273a5aae 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
@@ -16,6 +16,7 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.register_max = 64,
.thread_count = 128,
.shader_core_count = 1,
+ .nn_core_count = 0,
.vertex_cache_size = 8,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,
@@ -47,6 +48,7 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.register_max = 64,
.thread_count = 512,
.shader_core_count = 2,
+ .nn_core_count = 0,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,
@@ -78,6 +80,7 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.register_max = 64,
.thread_count = 512,
.shader_core_count = 2,
+ .nn_core_count = 0,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 1,
@@ -109,6 +112,7 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.register_max = 64,
.thread_count = 1024,
.shader_core_count = 4,
+ .nn_core_count = 0,
.vertex_cache_size = 16,
.vertex_output_buffer_size = 1024,
.pixel_pipes = 2,
--
2.38.1
next prev parent reply other threads:[~2022-12-01 10:31 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 10:30 [PATCH v5 0/7] Support for the NPU in Vim3 Tomeu Vizoso
2022-12-01 10:30 ` [PATCH v5 1/7] dt-bindings: reset: meson-g12a: Add missing NNA reset Tomeu Vizoso
2022-12-01 12:32 ` Neil Armstrong
2022-12-01 22:22 ` Martin Blumenstingl
2022-12-01 10:30 ` [PATCH v5 2/7] dt-bindings: power: Add G12A NNA power domain Tomeu Vizoso
2022-12-01 22:22 ` Martin Blumenstingl
2022-12-01 10:30 ` [PATCH v5 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D Tomeu Vizoso
2022-12-01 22:43 ` Martin Blumenstingl
2022-12-02 8:53 ` Neil Armstrong
2022-12-01 10:30 ` [PATCH v5 4/7] arm64: dts: Add DT node for the VIPNano-QI on the A311D Tomeu Vizoso
2022-12-01 22:33 ` Martin Blumenstingl
2022-12-02 8:57 ` Neil Armstrong
2022-12-01 10:30 ` Tomeu Vizoso [this message]
2022-12-01 18:01 ` [PATCH v5 5/7] drm/etnaviv: Add nn_core_count to chip feature struct Lucas Stach
2022-12-01 10:30 ` [PATCH v5 6/7] drm/etnaviv: Warn when probing on NPUs Tomeu Vizoso
2022-12-01 10:30 ` [PATCH v5 7/7] drm/etnaviv: add HWDB entry for VIPNano-QI.7120.0055 Tomeu Vizoso
2023-02-01 13:26 ` Lucas Stach
2023-02-01 15:25 ` Tomeu Vizoso
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