From: Kim Phillips <kim.phillips@amd.com>
To: <x86@kernel.org>
Cc: Kim Phillips <kim.phillips@amd.com>,
Babu Moger <Babu.Moger@amd.com>, Borislav Petkov <bp@alien8.de>,
Borislav Petkov <bp@amd.com>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>, Ingo Molnar <mingo@redhat.com>,
Joao Martins <joao.m.martins@oracle.com>,
Jonathan Corbet <corbet@lwn.net>,
"Konrad Rzeszutek Wilk" <konrad.wilk@oracle.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Thomas Gleixner <tglx@linutronix.de>,
David Woodhouse <dwmw@amazon.co.uk>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Juergen Gross <jgross@suse.com>,
Peter Zijlstra <peterz@infradead.org>,
Tony Luck <tony.luck@intel.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Alexey Kardashevskiy <aik@amd.com>, <kvm@vger.kernel.org>,
<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v5 3/7] x86/cpu: Make X86_FEATURE_LFENCE_RDTSC a scattered feature bit
Date: Mon, 5 Dec 2022 17:32:31 -0600 [thread overview]
Message-ID: <20221205233235.622491-4-kim.phillips@amd.com> (raw)
In-Reply-To: <20221205233235.622491-1-kim.phillips@amd.com>
It's a part of the CPUID 0x80000021 leaf, and will be grouped
with other feature bits to being propagated via kvm_set_cpu_caps()
instead of open-coding them in __do_cpuid_func().
Unlike the other CPUID 0x80000021 EAX feature bits,
X86_FEATURE_LFENCE_RDTSC already had an entry in cpufeatures.h.
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
---
arch/x86/kernel/cpu/scattered.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index d0734cc19d37..caa03466cd9e 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -46,6 +46,7 @@ static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
{ X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
{ X86_FEATURE_NO_NESTED_DATA_BP,CPUID_EAX, 0, 0x80000021, 0 },
+ { X86_FEATURE_LFENCE_RDTSC, CPUID_EAX, 2, 0x80000021, 0 },
{ X86_FEATURE_NULL_SEL_CLR_BASE,CPUID_EAX, 6, 0x80000021, 0 },
{ X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 },
{ X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 },
--
2.34.1
next prev parent reply other threads:[~2022-12-05 23:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-05 23:32 [PATCH v5 0/7] x86/cpu, kvm: Support AMD Automatic IBRS Kim Phillips
2022-12-05 23:32 ` [PATCH v5 1/7] x86/cpu: Define a scattered No Nested Data Breakpoints feature bit Kim Phillips
2022-12-05 23:32 ` [PATCH v5 2/7] x86/cpu: Define a scattered Null Selector Clears Base " Kim Phillips
2022-12-05 23:32 ` Kim Phillips [this message]
2022-12-27 10:51 ` [PATCH v5 3/7] x86/cpu: Make X86_FEATURE_LFENCE_RDTSC a scattered " Borislav Petkov
2022-12-05 23:32 ` [PATCH v5 4/7] x86/cpu, kvm: Move CPUID 0x80000021 EAX feature bits propagation to kvm_set_cpu_caps() Kim Phillips
2022-12-05 23:32 ` [PATCH v5 5/7] x86/cpu: Define a scattered AMD Automatic IBRS feature bit Kim Phillips
2022-12-05 23:32 ` [PATCH v5 6/7] x86/cpu: Support AMD Automatic IBRS Kim Phillips
2022-12-05 23:32 ` [PATCH v5 7/7] x86/cpu, kvm: Propagate the AMD Automatic IBRS feature to the guest Kim Phillips
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