Hi Hal, I love your patch! Perhaps something to improve: [auto build test WARNING on 830b3c68c1fb1e9176028d02ef86f3cf76aa2476] url: https://github.com/intel-lab-lkp/linux/commits/Hal-Feng/Basic-clock-and-reset-support-for-StarFive-JH7110-RISC-V-SoC/20221220-090131 base: 830b3c68c1fb1e9176028d02ef86f3cf76aa2476 patch link: https://lore.kernel.org/r/20221220005054.34518-10-hal.feng%40starfivetech.com patch subject: [PATCH v3 09/11] clk: starfive: Add StarFive JH7110 system clock driver config: riscv-randconfig-s042-20221218 compiler: riscv64-linux-gcc (GCC) 12.1.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # apt-get install sparse # sparse version: v0.6.4-39-gce1a6720-dirty # https://github.com/intel-lab-lkp/linux/commit/59e8d6aa846044f03cd50f806a9ed0577d1a6b70 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Hal-Feng/Basic-clock-and-reset-support-for-StarFive-JH7110-RISC-V-SoC/20221220-090131 git checkout 59e8d6aa846044f03cd50f806a9ed0577d1a6b70 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=riscv olddefconfig COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=riscv SHELL=/bin/bash drivers/clk/starfive/ drivers/reset/starfive/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot sparse warnings: (new ones prefixed by >>) WARNING: invalid argument to '-march': '_zihintpause' >> drivers/clk/starfive/clk-starfive-jh7110-sys.c:359:40: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void *data @@ got void [noderef] __iomem *base @@ drivers/clk/starfive/clk-starfive-jh7110-sys.c:359:40: sparse: expected void *data drivers/clk/starfive/clk-starfive-jh7110-sys.c:359:40: sparse: got void [noderef] __iomem *base vim +359 drivers/clk/starfive/clk-starfive-jh7110-sys.c 340 341 static int __init jh7110_syscrg_probe(struct platform_device *pdev) 342 { 343 struct jh71x0_clk_priv *priv; 344 unsigned int idx; 345 int ret; 346 347 priv = devm_kzalloc(&pdev->dev, 348 struct_size(priv, reg, JH7110_SYSCLK_PLL0_OUT), 349 GFP_KERNEL); 350 if (!priv) 351 return -ENOMEM; 352 353 spin_lock_init(&priv->rmw_lock); 354 priv->dev = &pdev->dev; 355 priv->base = devm_platform_ioremap_resource(pdev, 0); 356 if (IS_ERR(priv->base)) 357 return PTR_ERR(priv->base); 358 > 359 dev_set_drvdata(priv->dev, priv->base); 360 361 /* 24MHz -> 1250.0MHz */ 362 priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", 363 "osc", 0, 625, 12); 364 if (IS_ERR(priv->pll[0])) 365 return PTR_ERR(priv->pll[0]); 366 367 /* 24MHz -> 1066.0MHz */ 368 priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", 369 "osc", 0, 533, 12); 370 if (IS_ERR(priv->pll[1])) 371 return PTR_ERR(priv->pll[1]); 372 373 /* 24MHz -> 1188.0MHz */ 374 priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", 375 "osc", 0, 99, 2); 376 if (IS_ERR(priv->pll[2])) 377 return PTR_ERR(priv->pll[2]); 378 379 for (idx = 0; idx < JH7110_SYSCLK_PLL0_OUT; idx++) { 380 u32 max = jh7110_sysclk_data[idx].max; 381 struct clk_parent_data parents[4] = {}; 382 struct clk_init_data init = { 383 .name = jh7110_sysclk_data[idx].name, 384 .ops = starfive_jh71x0_clk_ops(max), 385 .parent_data = parents, 386 .num_parents = 387 ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, 388 .flags = jh7110_sysclk_data[idx].flags, 389 }; 390 struct jh71x0_clk *clk = &priv->reg[idx]; 391 unsigned int i; 392 393 for (i = 0; i < init.num_parents; i++) { 394 unsigned int pidx = jh7110_sysclk_data[idx].parents[i]; 395 396 if (pidx < JH7110_SYSCLK_PLL0_OUT) 397 parents[i].hw = &priv->reg[pidx].hw; 398 else if (pidx < JH7110_SYSCLK_END) 399 parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT]; 400 else if (pidx == JH7110_SYSCLK_OSC) 401 parents[i].fw_name = "osc"; 402 else if (pidx == JH7110_SYSCLK_GMAC1_RMII_REFIN) 403 parents[i].fw_name = "gmac1_rmii_refin"; 404 else if (pidx == JH7110_SYSCLK_GMAC1_RGMII_RXIN) 405 parents[i].fw_name = "gmac1_rgmii_rxin"; 406 else if (pidx == JH7110_SYSCLK_I2STX_BCLK_EXT) 407 parents[i].fw_name = "i2stx_bclk_ext"; 408 else if (pidx == JH7110_SYSCLK_I2STX_LRCK_EXT) 409 parents[i].fw_name = "i2stx_lrck_ext"; 410 else if (pidx == JH7110_SYSCLK_I2SRX_BCLK_EXT) 411 parents[i].fw_name = "i2srx_bclk_ext"; 412 else if (pidx == JH7110_SYSCLK_I2SRX_LRCK_EXT) 413 parents[i].fw_name = "i2srx_lrck_ext"; 414 else if (pidx == JH7110_SYSCLK_TDM_EXT) 415 parents[i].fw_name = "tdm_ext"; 416 else if (pidx == JH7110_SYSCLK_MCLK_EXT) 417 parents[i].fw_name = "mclk_ext"; 418 } 419 420 clk->hw.init = &init; 421 clk->idx = idx; 422 clk->max_div = max & JH71X0_CLK_DIV_MASK; 423 424 ret = devm_clk_hw_register(&pdev->dev, &clk->hw); 425 if (ret) 426 return ret; 427 } 428 429 ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_sysclk_get, priv); 430 if (ret) 431 return ret; 432 433 return jh7110_reset_controller_register(priv, "reset-sys", 0); 434 } 435 -- 0-DAY CI Kernel Test Service https://01.org/lkp