[PATCH 1/3] arm64: dts: qcom: sm8250: Pad addresses to 8 hex digits

[PATCH 1/3] arm64: dts: qcom: sm8250: Pad addresses to 8 hex digits

[Konrad Dybcio]

Some addresses were 7-hex-digits long. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index a3aa85a32bf8..3b3ea380c6e6 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2284,7 +2284,7 @@ rxmacro: rxmacro@3200000 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&rx_swr_active>;
 			compatible = "qcom,sm8250-lpass-rx-macro";
-			reg = <0 0x3200000 0 0x1000>;
+			reg = <0 0x03200000 0 0x1000>;
 			status = "disabled";
 
 			clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
@@ -2302,7 +2302,7 @@ rxmacro: rxmacro@3200000 {
 		};
 
 		swr1: soundwire-controller@3210000 {
-			reg = <0 0x3210000 0 0x2000>;
+			reg = <0 0x03210000 0 0x2000>;
 			compatible = "qcom,soundwire-v1.5.1";
 			status = "disabled";
 			interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
@@ -2331,7 +2331,7 @@ txmacro: txmacro@3220000 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&tx_swr_active>;
 			compatible = "qcom,sm8250-lpass-tx-macro";
-			reg = <0 0x3220000 0 0x1000>;
+			reg = <0 0x03220000 0 0x1000>;
 			status = "disabled";
 
 			clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
@@ -2352,7 +2352,7 @@ txmacro: txmacro@3220000 {
 
 		/* tx macro */
 		swr2: soundwire-controller@3230000 {
-			reg = <0 0x3230000 0 0x2000>;
+			reg = <0 0x03230000 0 0x2000>;
 			compatible = "qcom,soundwire-v1.5.1";
 			interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "core";
-- 
2.39.0

[PATCH 2/3] arm64: dts: qcom: sm8250: Touch up audio hw nodes

[Konrad Dybcio]

- Expand long clock-names into vertical lists
- Shuffle properties around:
  - Make sure compatible goes first and status goes last
  - Make property order consistent between similar nodes
- Fix up indentation
- Remove stray newlines
- Remove a redundant comment about swr2 being associated with TX macro
  (it's obvious by looking at the label property 10 lines below)
- Change unnecessary interrupts-extended to interrupts
- Disable SWR0 and WSA macro by default and enable them on SM8250 MTP and
  RB5, which were the only users
- Remove stray #address/size-cells from txmacro, as it's not even
  supposed to have children

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/qrb5165-rb5.dts |  6 ++
 arch/arm64/boot/dts/qcom/sm8250-mtp.dts  |  6 ++
 arch/arm64/boot/dts/qcom/sm8250.dtsi     | 82 +++++++++++++-----------
 3 files changed, 58 insertions(+), 36 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index 8c64cb060e21..6802d36fb20c 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -1007,6 +1007,8 @@ can@0 {
 };
 
 &swr0 {
+	status = "okay";
+
 	left_spkr: speaker@0,3 {
 		compatible = "sdw10217211000";
 		reg = <0 3>;
@@ -1322,6 +1324,10 @@ &venus {
 	status = "okay";
 };
 
+&wsamacro {
+	status = "okay";
+};
+
 /* PINCTRL - additions to nodes defined in sm8250.dtsi */
 &qup_spi0_cs_gpio {
 	drive-strength = <6>;
diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
index 3ed8c84e25b8..436e280ed3fc 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
@@ -757,6 +757,8 @@ codec {
 };
 
 &swr0 {
+	status = "okay";
+
 	left_spkr: speaker@0,3 {
 		compatible = "sdw10217211000";
 		reg = <0 3>;
@@ -890,3 +892,7 @@ &usb_2_qmpphy {
 &venus {
 	status = "okay";
 };
+
+&wsamacro {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 3b3ea380c6e6..dffce681d417 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2223,21 +2223,26 @@ wsamacro: codec@3240000 {
 				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
 				 <&aoncc LPASS_CDC_VA_MCLK>,
 				 <&vamacro>;
+			clock-names = "mclk",
+				      "npl",
+				      "macro",
+				      "dcodec",
+				      "va",
+				      "fsgen";
 
-			clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
+			pinctrl-names = "default";
+			pinctrl-0 = <&wsa_swr_active>;
 
 			#clock-cells = <0>;
 			clock-frequency = <9600000>;
 			clock-output-names = "mclk";
 			#sound-dai-cells = <1>;
-
-			pinctrl-names = "default";
-			pinctrl-0 = <&wsa_swr_active>;
+			status = "disabled";
 		};
 
 		swr0: soundwire-controller@3250000 {
-			reg = <0 0x03250000 0 0x2000>;
 			compatible = "qcom,soundwire-v1.5.1";
+			reg = <0 0x03250000 0 0x2000>;
 			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&wsamacro>;
 			clock-names = "iface";
@@ -2253,6 +2258,7 @@ swr0: soundwire-controller@3250000 {
 			#sound-dai-cells = <1>;
 			#address-cells = <2>;
 			#size-cells = <0>;
+			status = "disabled";
 		};
 
 		audiocc: clock-controller@3300000 {
@@ -2260,8 +2266,8 @@ audiocc: clock-controller@3300000 {
 			reg = <0 0x03300000 0 0x30000>;
 			#clock-cells = <1>;
 			clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				<&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
 			clock-names = "core", "audio", "bus";
 		};
 
@@ -2269,9 +2275,8 @@ vamacro: codec@3370000 {
 			compatible = "qcom,sm8250-lpass-va-macro";
 			reg = <0 0x03370000 0 0x1000>;
 			clocks = <&aoncc LPASS_CDC_VA_MCLK>,
-				<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
-
+				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
 			clock-names = "mclk", "macro", "dcodec";
 
 			#clock-cells = <0>;
@@ -2281,34 +2286,37 @@ vamacro: codec@3370000 {
 		};
 
 		rxmacro: rxmacro@3200000 {
-			pinctrl-names = "default";
-			pinctrl-0 = <&rx_swr_active>;
 			compatible = "qcom,sm8250-lpass-rx-macro";
 			reg = <0 0x03200000 0 0x1000>;
-			status = "disabled";
-
 			clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				<&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				<&vamacro>;
+				 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&vamacro>;
+			clock-names = "mclk",
+				      "npl",
+				      "macro",
+				      "dcodec",
+				      "fsgen";
 
-			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
+			pinctrl-names = "default";
+			pinctrl-0 = <&rx_swr_active>;
 
 			#clock-cells = <0>;
 			clock-frequency = <9600000>;
 			clock-output-names = "mclk";
 			#sound-dai-cells = <1>;
+			status = "disabled";
 		};
 
 		swr1: soundwire-controller@3210000 {
-			reg = <0 0x03210000 0 0x2000>;
 			compatible = "qcom,soundwire-v1.5.1";
-			status = "disabled";
+			reg = <0 0x03210000 0 0x2000>;
 			interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&rxmacro>;
 			clock-names = "iface";
 			label = "RX";
+
 			qcom,din-ports = <0>;
 			qcom,dout-ports = <5>;
 
@@ -2325,45 +2333,45 @@ swr1: soundwire-controller@3210000 {
 			#sound-dai-cells = <1>;
 			#address-cells = <2>;
 			#size-cells = <0>;
+			status = "disabled";
 		};
 
 		txmacro: txmacro@3220000 {
-			pinctrl-names = "default";
-			pinctrl-0 = <&tx_swr_active>;
 			compatible = "qcom,sm8250-lpass-tx-macro";
 			reg = <0 0x03220000 0 0x1000>;
-			status = "disabled";
-
 			clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
 				 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
 				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
 				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
 				 <&vamacro>;
+			clock-names = "mclk",
+				      "npl",
+				      "macro",
+				      "dcodec",
+				      "fsgen";
 
-			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
+			pinctrl-names = "default";
+			pinctrl-0 = <&tx_swr_active>;
 
 			#clock-cells = <0>;
 			clock-frequency = <9600000>;
 			clock-output-names = "mclk";
-			#address-cells = <2>;
-			#size-cells = <2>;
 			#sound-dai-cells = <1>;
+			status = "disabled";
 		};
 
-		/* tx macro */
 		swr2: soundwire-controller@3230000 {
-			reg = <0 0x03230000 0 0x2000>;
 			compatible = "qcom,soundwire-v1.5.1";
-			interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0 0x03230000 0 0x2000>;
+			interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "core";
-			status = "disabled";
-
 			clocks = <&txmacro>;
 			clock-names = "iface";
 			label = "TX";
 
 			qcom,din-ports = <5>;
 			qcom,dout-ports = <0>;
+
 			qcom,ports-sinterval-low =	/bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
 			qcom,ports-offset1 =		/bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
 			qcom,ports-offset2 =		/bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
@@ -2373,9 +2381,11 @@ swr2: soundwire-controller@3230000 {
 			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
 			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
 			qcom,ports-lane-control =	/bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
+
 			#sound-dai-cells = <1>;
 			#address-cells = <2>;
 			#size-cells = <0>;
+			status = "disabled";
 		};
 
 		aoncc: clock-controller@3380000 {
@@ -2383,8 +2393,8 @@ aoncc: clock-controller@3380000 {
 			reg = <0 0x03380000 0 0x40000>;
 			#clock-cells = <1>;
 			clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				<&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
 			clock-names = "core", "audio", "bus";
 		};
 
@@ -2397,7 +2407,7 @@ lpass_tlmm: pinctrl@33c0000{
 			gpio-ranges = <&lpass_tlmm 0 0 14>;
 
 			clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
 			clock-names = "core", "audio";
 
 			wsa_swr_active: wsa-swr-active-state {
-- 
2.39.0

[PATCH 3/3] arm64: dts: qcom: sm8250: Sort audio hw nodes

[Konrad Dybcio]

Half of the audio hardware nodes were not sorted properly. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 142 +++++++++++++--------------
 1 file changed, 71 insertions(+), 71 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index dffce681d417..0b6a6a809503 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2214,77 +2214,6 @@ tcsr_mutex: hwlock@1f40000 {
 			#hwlock-cells = <1>;
 		};
 
-		wsamacro: codec@3240000 {
-			compatible = "qcom,sm8250-lpass-wsa-macro";
-			reg = <0 0x03240000 0 0x1000>;
-			clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
-				 <&audiocc LPASS_CDC_WSA_NPL>,
-				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				 <&aoncc LPASS_CDC_VA_MCLK>,
-				 <&vamacro>;
-			clock-names = "mclk",
-				      "npl",
-				      "macro",
-				      "dcodec",
-				      "va",
-				      "fsgen";
-
-			pinctrl-names = "default";
-			pinctrl-0 = <&wsa_swr_active>;
-
-			#clock-cells = <0>;
-			clock-frequency = <9600000>;
-			clock-output-names = "mclk";
-			#sound-dai-cells = <1>;
-			status = "disabled";
-		};
-
-		swr0: soundwire-controller@3250000 {
-			compatible = "qcom,soundwire-v1.5.1";
-			reg = <0 0x03250000 0 0x2000>;
-			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&wsamacro>;
-			clock-names = "iface";
-
-			qcom,din-ports = <2>;
-			qcom,dout-ports = <6>;
-
-			qcom,ports-sinterval-low =	/bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
-			qcom,ports-offset1 =		/bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
-			qcom,ports-offset2 =		/bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
-			qcom,ports-block-pack-mode =	/bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
-
-			#sound-dai-cells = <1>;
-			#address-cells = <2>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		audiocc: clock-controller@3300000 {
-			compatible = "qcom,sm8250-lpass-audiocc";
-			reg = <0 0x03300000 0 0x30000>;
-			#clock-cells = <1>;
-			clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
-			clock-names = "core", "audio", "bus";
-		};
-
-		vamacro: codec@3370000 {
-			compatible = "qcom,sm8250-lpass-va-macro";
-			reg = <0 0x03370000 0 0x1000>;
-			clocks = <&aoncc LPASS_CDC_VA_MCLK>,
-				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
-				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
-			clock-names = "mclk", "macro", "dcodec";
-
-			#clock-cells = <0>;
-			clock-frequency = <9600000>;
-			clock-output-names = "fsgen";
-			#sound-dai-cells = <1>;
-		};
-
 		rxmacro: rxmacro@3200000 {
 			compatible = "qcom,sm8250-lpass-rx-macro";
 			reg = <0 0x03200000 0 0x1000>;
@@ -2388,6 +2317,77 @@ swr2: soundwire-controller@3230000 {
 			status = "disabled";
 		};
 
+		wsamacro: codec@3240000 {
+			compatible = "qcom,sm8250-lpass-wsa-macro";
+			reg = <0 0x03240000 0 0x1000>;
+			clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
+				 <&audiocc LPASS_CDC_WSA_NPL>,
+				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&aoncc LPASS_CDC_VA_MCLK>,
+				 <&vamacro>;
+			clock-names = "mclk",
+				      "npl",
+				      "macro",
+				      "dcodec",
+				      "va",
+				      "fsgen";
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&wsa_swr_active>;
+
+			#clock-cells = <0>;
+			clock-frequency = <9600000>;
+			clock-output-names = "mclk";
+			#sound-dai-cells = <1>;
+			status = "disabled";
+		};
+
+		swr0: soundwire-controller@3250000 {
+			compatible = "qcom,soundwire-v1.5.1";
+			reg = <0 0x03250000 0 0x2000>;
+			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&wsamacro>;
+			clock-names = "iface";
+
+			qcom,din-ports = <2>;
+			qcom,dout-ports = <6>;
+
+			qcom,ports-sinterval-low =	/bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
+			qcom,ports-offset1 =		/bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
+			qcom,ports-offset2 =		/bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
+			qcom,ports-block-pack-mode =	/bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
+
+			#sound-dai-cells = <1>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		audiocc: clock-controller@3300000 {
+			compatible = "qcom,sm8250-lpass-audiocc";
+			reg = <0 0x03300000 0 0x30000>;
+			#clock-cells = <1>;
+			clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "core", "audio", "bus";
+		};
+
+		vamacro: codec@3370000 {
+			compatible = "qcom,sm8250-lpass-va-macro";
+			reg = <0 0x03370000 0 0x1000>;
+			clocks = <&aoncc LPASS_CDC_VA_MCLK>,
+				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "mclk", "macro", "dcodec";
+
+			#clock-cells = <0>;
+			clock-frequency = <9600000>;
+			clock-output-names = "fsgen";
+			#sound-dai-cells = <1>;
+		};
+
 		aoncc: clock-controller@3380000 {
 			compatible = "qcom,sm8250-lpass-aoncc";
 			reg = <0 0x03380000 0 0x40000>;
-- 
2.39.0

Re: [PATCH 2/3] arm64: dts: qcom: sm8250: Touch up audio hw nodes

[Krzysztof Kozlowski]

On 30/12/2022 14:50, Konrad Dybcio wrote:
> - Expand long clock-names into vertical lists
> - Shuffle properties around:
>   - Make sure compatible goes first and status goes last
>   - Make property order consistent between similar nodes
> - Fix up indentation
> - Remove stray newlines
> - Remove a redundant comment about swr2 being associated with TX macro
>   (it's obvious by looking at the label property 10 lines below)
> - Change unnecessary interrupts-extended to interrupts
> - Disable SWR0 and WSA macro by default and enable them on SM8250 MTP and
>   RB5, which were the only users
> - Remove stray #address/size-cells from txmacro, as it's not even
>   supposed to have children

You duplicate here some work:
https://lore.kernel.org/all/20221225115844.55126-4-krzysztof.kozlowski@linaro.org/

and maybe:
https://lore.kernel.org/all/167233461775.1099840.3444272939352778399.b4-ty@kernel.org/

If you wish to avoid trivial cleanup conflicts, feel free to poke to my
pending branch:
https://github.com/krzk/linux/commits/pending/dt-bindings-qcom-new-and-fixes-for-warnings-linux-next

Also, this is a mixture of non-functional changes (re-ordering,
whitespace) with something close to functional (interrupts-extended ->
interrupts, disabling nodes in DTSI). These should be split.



Best regards,
Krzysztof

Re: [PATCH 3/3] arm64: dts: qcom: sm8250: Sort audio hw nodes

[Krzysztof Kozlowski]

On 30/12/2022 14:50, Konrad Dybcio wrote:
> Half of the audio hardware nodes were not sorted properly. Fix that.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---


Just a note:

> +		wsamacro: codec@3240000 {
> +			compatible = "qcom,sm8250-lpass-wsa-macro";
> +			reg = <0 0x03240000 0 0x1000>;
> +			clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
> +				 <&audiocc LPASS_CDC_WSA_NPL>,
> +				 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> +				 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> +				 <&aoncc LPASS_CDC_VA_MCLK>,
> +				 <&vamacro>;
> +			clock-names = "mclk",
> +				      "npl",
> +				      "macro",
> +				      "dcodec",
> +				      "va",
> +				      "fsgen";
> +
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&wsa_swr_active>;
> +
> +			#clock-cells = <0>;
> +			clock-frequency = <9600000>;

This will conflict:
https://lore.kernel.org/all/20221224154255.43499-3-krzysztof.kozlowski@linaro.org/

https://lore.kernel.org/all/20221225115844.55126-3-krzysztof.kozlowski@linaro.org/

Best regards,
Krzysztof

Re: [PATCH 2/3] arm64: dts: qcom: sm8250: Touch up audio hw nodes

[Konrad Dybcio]

On 30.12.2022 17:08, Krzysztof Kozlowski wrote:
> On 30/12/2022 14:50, Konrad Dybcio wrote:
>> - Expand long clock-names into vertical lists
>> - Shuffle properties around:
>>   - Make sure compatible goes first and status goes last
>>   - Make property order consistent between similar nodes
>> - Fix up indentation
>> - Remove stray newlines
>> - Remove a redundant comment about swr2 being associated with TX macro
>>   (it's obvious by looking at the label property 10 lines below)
>> - Change unnecessary interrupts-extended to interrupts
>> - Disable SWR0 and WSA macro by default and enable them on SM8250 MTP and
>>   RB5, which were the only users
>> - Remove stray #address/size-cells from txmacro, as it's not even
>>   supposed to have children
> 
> You duplicate here some work:
> https://lore.kernel.org/all/20221225115844.55126-4-krzysztof.kozlowski@linaro.org/
> 
> and maybe:
> https://lore.kernel.org/all/167233461775.1099840.3444272939352778399.b4-ty@kernel.org/
> 
> If you wish to avoid trivial cleanup conflicts, feel free to poke to my
> pending branch:
> https://github.com/krzk/linux/commits/pending/dt-bindings-qcom-new-and-fixes-for-warnings-linux-next
> 
> Also, this is a mixture of non-functional changes (re-ordering,
> whitespace) with something close to functional (interrupts-extended ->
> interrupts, disabling nodes in DTSI). These should be split.
Thanks for pointing this out, I'll resubmit these soon!

Konrad
> 
> 
> 
> Best regards,
> Krzysztof
> 

Re: (subset) [PATCH 1/3] arm64: dts: qcom: sm8250: Pad addresses to 8 hex digits

[Bjorn Andersson]

On Fri, 30 Dec 2022 14:50:42 +0100, Konrad Dybcio wrote:
> Some addresses were 7-hex-digits long. Fix that.
> 
> 

Applied, thanks!

[1/3] arm64: dts: qcom: sm8250: Pad addresses to 8 hex digits
      commit: d8b4ee9379e4b6df44bbaf6020461514b401b8f6

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>