From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D57BAC54EAA for ; Mon, 30 Jan 2023 21:40:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231402AbjA3Vk1 (ORCPT ); Mon, 30 Jan 2023 16:40:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230526AbjA3VkQ (ORCPT ); Mon, 30 Jan 2023 16:40:16 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA0AC1727 for ; Mon, 30 Jan 2023 13:40:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675114815; x=1706650815; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=voF6jjo5dj3mRofutynhvBZdyYRA2mgyQE5q7XMzfyI=; b=IGhswbX6MwpHgvW1cRRt3pbfTQqQApeymmgRsgLmalGvnNteEuuAFZVL 8N/6WHsaNjI9NTlmRkBoSFpB+Jjg+rt/jIDjT2ADZ08fwGFz/vkbwObTa 3WgPgo5CbWNKXDYLyg88MULdv4fTETRNYBR/2/RjiSQ18mfYqz1SeyXlz k6mETPivLePnCNVrDqyj/gCU7UqSk5tcvVx8wlKYaCbcRzrcfvUGklcc5 nPVqcMg118EzPqluxD17bMiC+rCIjWuMflYTcso22mxZQRZVXuvXoFFND NKSwWexDfaGhNhNYYtZkwnCAyxFtYhjDU7kHyoGPwyYGeapJ0jSDXuGBl A==; X-IronPort-AV: E=McAfee;i="6500,9779,10606"; a="328955530" X-IronPort-AV: E=Sophos;i="5.97,259,1669104000"; d="scan'208";a="328955530" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2023 13:40:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10606"; a="696571870" X-IronPort-AV: E=Sophos;i="5.97,259,1669104000"; d="scan'208";a="696571870" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2023 13:40:12 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: Ashok Raj , Tony Luck , LKML , x86 , Ingo Molnar , Dave Hansen , Alison Schofield , Reinette Chatre , Tom Lendacky , Stefan Talpalaru , David Woodhouse , Benjamin Herrenschmidt , Jonathan Corbet , "Rafael J . Wysocki" , Peter Zilstra , Andy Lutomirski , Andrew Cooper , Boris Ostrovsky , Martin Pohlack Subject: [Patch v3 Part2 5/9] x86/microcode: Move late load warning to the same function that taints kernel Date: Mon, 30 Jan 2023 13:39:51 -0800 Message-Id: <20230130213955.6046-6-ashok.raj@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230130213955.6046-1-ashok.raj@intel.com> References: <20230130213955.6046-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Late microcode loading issues a warning and taints the kernel. Tainting the kernel and emitting the warning happens in two different functions. The upcoming support for safe late loading under certain conditions needs to prevent both the warning and the tainting when the safe conditions are met. That would require to hand the result of the safe condition check into the function which emits the warning. To avoid this awkward construct, move the warning into reload_store() next to the taint() invocation as that is also the function which will later contain the safe condition check. No functional change. Signed-off-by: Ashok Raj Reviewed-by: Tony Luck Cc: LKML Cc: x86 Cc: Ingo Molnar Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner (Intel) Cc: Tom Lendacky Cc: Stefan Talpalaru Cc: David Woodhouse Cc: Benjamin Herrenschmidt Cc: Jonathan Corbet Cc: Rafael J. Wysocki Cc: Peter Zilstra (Intel) Cc: Andy Lutomirski Cc: Andrew Cooper Cc: Boris Ostrovsky Cc: Martin Pohlack --- arch/x86/kernel/cpu/microcode/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 8452fad89bf6..bff566c05f46 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -442,9 +442,6 @@ static int microcode_reload_late(void) int old = boot_cpu_data.microcode, ret; struct cpuinfo_x86 prev_info; - pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); - pr_err("You should switch to early loading, if possible.\n"); - atomic_set(&late_cpus_in, 0); atomic_set(&late_cpus_out, 0); @@ -487,6 +484,9 @@ static ssize_t reload_store(struct device *dev, if (ret) goto put; + pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); + pr_err("You should switch to early loading, if possible.\n"); + tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); if (tmp_ret != UCODE_NEW) { ret = size; -- 2.37.2