From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2622AC636CC for ; Mon, 20 Feb 2023 11:15:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231834AbjBTLPP (ORCPT ); Mon, 20 Feb 2023 06:15:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231701AbjBTLO6 (ORCPT ); Mon, 20 Feb 2023 06:14:58 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03CED1A962; Mon, 20 Feb 2023 03:14:36 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 31KBEVhc121327; Mon, 20 Feb 2023 05:14:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1676891671; bh=5EdSVxOwJdEk1EPvR7PTLjvZBWkus3YudnkOOyqcnZg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RY6Hy+vJpqhxL9UMFILckw6rRUQ8Gdd/t2Ix88C3hTc3BbzxBX0vc+TcwrMgM9Sou jXHFM8QeS8sl2OsPa6E+/nPtF06RuWMFVd8xyDiX/swJKZE2TfvmpFufY79Wrj0K9/ 61x2eSoT9EzO9RvbAQhQyylCWnBRS0kYsti0Xlq4= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 31KBEUsI128028 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 20 Feb 2023 05:14:30 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Mon, 20 Feb 2023 05:14:30 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Mon, 20 Feb 2023 05:14:30 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31KBE986068490; Mon, 20 Feb 2023 05:14:27 -0600 From: Ravi Gunasekaran To: , , , , , , , CC: , , Subject: [PATCH v9 5/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 Date: Mon, 20 Feb 2023 16:44:04 +0530 Message-ID: <20230220111408.9476-6-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230220111408.9476-1-r-gunasekaran@ti.com> References: <20230220111408.9476-1-r-gunasekaran@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Aswath Govindraju Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Link: https://lore.kernel.org/r/20221122101616.770050-5-mranostay@ti.com Signed-off-by: Ravi Gunasekaran --- I had reviewed this patch in the v5 series [1]. Since I'm taking over upstreaming this series, I removed the self Reviewed-by tag. Links: [1] - https://lore.kernel.org/all/71ce4ecd-2a50-c69d-28be-f1a8d769970e@ti.com/ .../dts/ti/k3-j721s2-common-proc-board.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index a7aa6cf08acd..c3a397484c70 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -9,6 +9,9 @@ #include "k3-j721s2-som-p0.dtsi" #include +#include +#include +#include / { compatible = "ti,j721s2-evm", "ti,j721s2"; @@ -296,6 +299,25 @@ phy-handle = <&phy0>; }; +&serdes_ln_ctrl { + idle-states = , , + , ; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; -- 2.17.1