From: Evan Green <evan@rivosinc.com>
To: Palmer Dabbelt <palmer@rivosinc.com>
Cc: heiko@sntech.de, Conor Dooley <conor@kernel.org>,
slewis@rivosinc.com, vineetg@rivosinc.com,
Evan Green <evan@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: [PATCH v3 4/7] dt-bindings: Add RISC-V misaligned access performance
Date: Tue, 21 Feb 2023 11:08:55 -0800 [thread overview]
Message-ID: <20230221190858.3159617-5-evan@rivosinc.com> (raw)
In-Reply-To: <20230221190858.3159617-1-evan@rivosinc.com>
From: Palmer Dabbelt <palmer@rivosinc.com>
This key allows device trees to specify the performance of misaligned
accesses to main memory regions from each CPU in the system.
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Evan Green <evan@rivosinc.com>
---
Changes in v3:
- Added | to description: to make dt-checker happy.
Documentation/devicetree/bindings/riscv/cpus.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6720764e765..f79e9e5c5ee9 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -85,6 +85,21 @@ properties:
$ref: "/schemas/types.yaml#/definitions/string"
pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
+ riscv,misaligned-access-performance:
+ description: |
+ Identifies the performance of misaligned memory accesses to main memory
+ regions. There are three flavors of unaligned access performance: "emulated"
+ means that misaligned accesses are emulated via software and thus
+ extremely slow, "slow" means that misaligned accesses are supported by
+ hardware but still slower that aligned accesses sequences, and "fast"
+ means that misaligned accesses are as fast or faster than the
+ cooresponding aligned accesses sequences.
+ $ref: "/schemas/types.yaml#/definitions/string"
+ enum:
+ - emulated
+ - slow
+ - fast
+
# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
timebase-frequency: false
--
2.25.1
next prev parent reply other threads:[~2023-02-21 19:10 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-21 19:08 [PATCH v3 0/7] RISC-V Hardware Probing User Interface Evan Green
2023-02-21 19:08 ` [PATCH v3 1/7] RISC-V: Move struct riscv_cpuinfo to new header Evan Green
2023-02-21 19:08 ` [PATCH v3 2/7] RISC-V: Add a syscall for HW probing Evan Green
2023-02-23 10:06 ` Arnd Bergmann
2023-03-30 18:30 ` Evan Green
2023-03-30 20:20 ` Heiko Stübner
2023-03-30 21:24 ` Evan Green
2023-03-31 13:21 ` Arnd Bergmann
2023-03-31 17:51 ` Evan Green
2023-02-27 22:19 ` Conor Dooley
2023-02-21 19:08 ` [PATCH v3 3/7] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Evan Green
2023-02-27 22:47 ` Conor Dooley
2023-03-03 0:56 ` Evan Green
2023-02-21 19:08 ` Evan Green [this message]
2023-02-27 22:57 ` [PATCH v3 4/7] dt-bindings: Add RISC-V misaligned access performance Conor Dooley
2023-02-28 14:57 ` Rob Herring
2023-02-21 19:08 ` [PATCH v3 5/7] RISC-V: hwprobe: Support probing of " Evan Green
2023-02-22 9:39 ` Joe Perches
2023-02-27 23:14 ` Conor Dooley
2023-02-21 19:08 ` [PATCH v3 6/7] selftests: Test the new RISC-V hwprobe interface Evan Green
2023-02-21 22:45 ` Mark Brown
2023-02-21 19:08 ` [PATCH v3 7/7] RISC-V: Add hwprobe vDSO function and data Evan Green
2023-02-21 21:17 ` kernel test robot
2023-02-22 6:55 ` kernel test robot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230221190858.3159617-5-evan@rivosinc.com \
--to=evan@rivosinc.com \
--cc=aou@eecs.berkeley.edu \
--cc=conor@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=heiko@sntech.de \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=palmer@rivosinc.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=slewis@rivosinc.com \
--cc=vineetg@rivosinc.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).