From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23A79C64ED8 for ; Sat, 25 Feb 2023 00:09:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229644AbjBYAJl (ORCPT ); Fri, 24 Feb 2023 19:09:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229513AbjBYAJi (ORCPT ); Fri, 24 Feb 2023 19:09:38 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8194365330; Fri, 24 Feb 2023 16:09:37 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 3487AB81D69; Sat, 25 Feb 2023 00:09:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0F218C433D2; Sat, 25 Feb 2023 00:09:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1677283774; bh=RECK9lZ040VDapm9jACPtKxrwZ3B3mKnm5zxgCnxXTI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=PIIzlP5FGApfltmgGEWd810KQSx8gJQZHS6T/9Q9mgE90h4HY1PePGrZ4T5b91O7U N7b1N+mhdVbL2Ge3ajierfPjSnSI4tVXqvlkQ2GosAYyFv0OjUueSbSrHxBiZvcbN1 fROVMQNC0fd5uGhxQMmJTInomULvbhqA1p0dKI/rAKXAtFZvyv3OBtmIGSkAZww0Hl 43HQ1V/Di793m7/vnjUX9Rr89wh+zdaxAIWOcuXg9lrBboZvAcokip2VBfMuyTgnux f3E3j/d0u0FCbtc+3UL08Z2y7CzX9Tv2SvE16fvf1z1dEEiTfQ+8c5el1+6qvWpJ1q rDbc9n1sqJrjw== Date: Fri, 24 Feb 2023 16:09:31 -0800 From: Josh Poimboeuf To: Borislav Petkov Cc: Kim Phillips , x86@kernel.org, Boris Ostrovsky , Dave Hansen , "H. Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , Paolo Bonzini , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , Alexey Kardashevskiy , kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v9 7/8] x86/cpu: Support AMD Automatic IBRS Message-ID: <20230225000931.wrednfun4jifkqau@treble> References: <20230124163319.2277355-1-kim.phillips@amd.com> <20230124163319.2277355-8-kim.phillips@amd.com> <20230224185257.o3mcmloei5zqu7wa@treble> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 24, 2023 at 11:51:17PM +0100, Borislav Petkov wrote: > On Fri, Feb 24, 2023 at 10:08:32PM +0100, Borislav Petkov wrote: > > On Fri, Feb 24, 2023 at 10:52:57AM -0800, Josh Poimboeuf wrote: > > > Doesn't this only enable it on the boot CPU? > > > > Whoops, you might be right. > > Actually, we stick that MSR - EFER - into the trampoline header and then > each AP gets it written to in arch/x86/realmode/rm/trampoline_64.S > > But this is only from code staring - I'll confirm this tomorrow. Ah, I had to stare it that for a bit to figure out how it works. setup_real_mode() reads MSR_EFER from the boot CPU and stores it in trampoline_header->efer. Then the other CPUs read that stored value in startup_32() and write it into their MSR. > And if so, we should at least put comments in that trampoline code so > that people do not remove the MSR writes. > > Or, actually, we should simply write it again because it is the init > path and not really a hot path but it should damn well make sure that > that bit gets set. Yeah, I think that would be good. Otherwise it's rather magical. That EFER MSR is a surprising place to put that bit. -- Josh