From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90F6EC64EC4 for ; Tue, 28 Feb 2023 21:55:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229720AbjB1VzJ (ORCPT ); Tue, 28 Feb 2023 16:55:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229486AbjB1VzD (ORCPT ); Tue, 28 Feb 2023 16:55:03 -0500 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4605F2F7B7 for ; Tue, 28 Feb 2023 13:54:54 -0800 (PST) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1pX7vm-0005hs-PZ; Tue, 28 Feb 2023 22:54:42 +0100 From: Heiko Stuebner To: palmer@dabbelt.com Cc: linux-riscv@lists.infradead.org, samuel@sholland.org, guoren@kernel.org, christoph.muellner@vrull.eu, heiko@sntech.de, conor.dooley@microchip.com, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH RFC 1/2] RISC-V: define the elements of the VCSR vector CSR Date: Tue, 28 Feb 2023 22:54:34 +0100 Message-Id: <20230228215435.3366914-2-heiko@sntech.de> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230228215435.3366914-1-heiko@sntech.de> References: <20230228215435.3366914-1-heiko@sntech.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Heiko Stuebner The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. Define constants for those to access the elements in a readable way. Signed-off-by: Heiko Stuebner --- arch/riscv/include/asm/csr.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index add51662b7c3..8b06f2472915 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -176,6 +176,11 @@ #define ENVCFG_CBIE_INV _AC(0x3, UL) #define ENVCFG_FIOM _AC(0x1, UL) +/* VCSR flags */ +#define VCSR_VXRM_MASK 3 +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXSAT_MASK 1 + /* symbolic CSR names: */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 -- 2.39.0